SUBJECT NAME: INTEGRATED ELECTRONICS NAME: muzzamil shah

ROLL NO: 2020-EE-076

SECTION: B

LAB NO # 11
Objective: Traces the Layout of complex scenarios using CMOS Technology in Microwind.
Task No.1: Design the schematic and layout of Full Adder using CMOS technology
and simulate its transient characteristics
LAYOUT:

OUTPUT:

DEPARTMENT OF ELECTRONIC ENGINEERING

SIR SYED UNIVERSITY OF ENGINEERING AND TECHNOLOGY
SUBJECT NAME: INTEGRATED ELECTRONICS NAME: muzzamil shah
ROLL NO: 2020-EE-076
SECTION: B

Task No.2: Design the schematic and layout of 4-bit Ripple Carry Adder, using
CMOS technology and simulate its transient characteristics.
LAYOUT:

OUTPUT:

DEPARTMENT OF ELECTRONIC ENGINEERING

SIR SYED UNIVERSITY OF ENGINEERING AND TECHNOLOGY