>>>>>>>>>>>>>>Prepare strictly topic-wise according to syllabus
UNIT-3 Prepare mealy and moore examples from book brown
UNIT-4
Asynchronous sequential circuit design: refer to the pages of book brown pg no:583-596
>Primitive flow table
A primitive flow table is a flow table with only one stable total state in each row. The
total state consists of the internal state combined with the input.
What is metastability?
>
Whenever there are setup and hold time violations in any flip-flop, it enters a
state where its output is unpredictable: this state is known as metastable state
(quasi stable state); at the end of metastable state, the flip-flop settles down to
either '1' or '0'. This whole process is known as metastability.
Race condition=
A race condition exists in an asynchronous sequential circuit when two or more binary
state variables change in response to a change in an input variable. – When
unequal delays are encountered, a race condition may cause the state variables to
change in an unpredictable manner.
critical and non critical races=
A critical race condition occurs when the sequence in which internal variables change
determines the final state of the machine. A non-critical race condition occurs when the
sequence in which internal variables' changes do not have any impact on the final state
of the machine.
Rest about it read from book Brown
Synchronizers
10.5.1 Synchronizers—Concept and Implementation
Even though a complete system may be designed in a synchronous fashion, it must still
communicate with the outside world, which is generally asynchronous. An asynchronous
input can change value at any time related to the clock edges of the synchronous system,
as is illustrated in Figure 10.50.
Consider a typical personal computer. All operations within the system are strictly
orchestrated by a central clock that provides a time reference. This reference determines
what happens within the computer system at any point in time. This synchronous computer
has to communicate with a human through the mouse or the keyboard, who has no
knowledge of this time reference and might decide to press a keyboard key at any point in
time. The way a synchronous system deals with such an asynchronous signal is to sample
or poll it at regular intervals and to check its value. If the sampling rate is high enough, no
transitions will be missed—this is known as the Nyquist criterion in the communication
community. However, it might happen that the signal is polled in the middle of a transition.
The resulting value is neither low or high but undefined. At that point, it is not clear
if the key was pressed or not. Feeding the undefined signal into the computer could be the
source of all types of trouble, especially when it is routed to different functions or gates
that might interpret it differently. For instance, one function might decide that the key is
pushed and start a certain action, while another function might lean the other way and
issue a competing command. This results in a conflict and a potential crash. Therefore, the
undefined state must be resolved in one way or another before it is interpreted further. It
does not really matter what decision is made, as long as a unique result is available. For
instance, it is either decided that the key is not yet pressed, which will be corrected in the
next poll of the keyboard, or it is concluded that the key is already pressed.
Thus, an asynchronous signal must be resolved to be either in the high or low state
before it is fed into the synchronous environment. A circuit that implements such a decision-
making function is called a synchronizer.
Architecture of CPLD (Xilinx/Altera). For this topic look book brown Pg 901 or from book ROTH
For PAL and PLA any net source
Practice numericals both (synchronous and asynchronous design) and theory from 2015 to 2018
questions papers (IPU)
