Scribd
Upload
26 views13 pages

Finite State Machine Design Essentials

1) The document discusses various finite state machine approaches including Moore and Mealy models, state diagrams, and examples of state machines for an abb sequence detector, mod-5 counter, and frequency detector. 2) It also covers topics like underspecification, overspecification, metastability, clock gating, glitches, pulse detection, and edge detection circuits. 3) Examples are provided to illustrate Moore to Mealy and Mealy to Moore conversions, synchronous and asynchronous counters, and the use of flip-flops, synchronizers, and oneshot circuits.

Uploaded by

PABBATHI BALAJI
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
26 views13 pages

Finite State Machine Design Essentials

1) The document discusses various finite state machine approaches including Moore and Mealy models, state diagrams, and examples of state machines for an abb sequence detector, mod-5 counter, and frequency detector. 2) It also covers topics like underspecification, overspecification, metastability, clock gating, glitches, pulse detection, and edge detection circuits. 3) Examples are provided to illustrate Moore to Mealy and Mealy to Moore conversions, synchronous and asynchronous counters, and the use of flip-flops, synchronizers, and oneshot circuits.

Uploaded by

PABBATHI BALAJI
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

FINITE STATE MACHINE APPROACH

---------------------------------------------------------------

Moore state machine example:


-----------------------------------------------
abb sequence detector:
Mealy model:
----------------------
...............Mod-5 counter from 001 to 101
...............in figure (g) and (f ) else part is implicitly expressed

Underspecified means all conditions are not covered

Another example of timed state diagram:


RTL code for all the three above cases

in figure(a) unnecessary in this case >= checking perfect one.


latch inferred and makes hardware more
underspecified complex

Note point:
----------------

Overspecified means morethan one state has possibilty to go at same time

if both a=1and b=1 in figure(a) then both B and C has possibilites so error

Another example:
----------------------------
4 types:
------------------
...unconditional
...conditional
...timed
...conditional timed

Moore to Mealy and Mealy to Moore conversion:

in simpler words

1)same o/ps
2)same next state

possible only in Moore to Mealy conversion

example:
Mealy to moore conversion:
----------------------------------------------
here states get splitted

In case (c) and (d) it is preferabble


To correcly design FSMs in hardware ....these are very essential.

D flipflops are common and also used in FPGA devices .

Transparent flipflop

Dff with rst ......asynchronous


Dff with clr .......synchronous

let assumed

then
so to avoid metastable condition we need to follow

if ‘d’ input changes in aperture window (forbidden region) then it leads to


metastablility and it takes one of the two paths (path1 or path2) to retain back to
normal state and it require some clock cycles.

To avoid this we use synchronisers .....two ways


two-stage synchroniser is used

Another example: it calculates frequency of input with respect to clk

Clock gating:
----------------------
above is bcoz one clk cycle delay between i/p and o/p.

Flipflop is negetive edge triggered as our circuit is postive triggered to avoid


METASTABILITY CONDITION (similar to verilog testbench...sampling at negegde).

Two flipflops are used in second case bcoz just observe clk which portion we want
to make zero .....to acheive it exacly we need to flipflops ....(observe q2 o/p)
Adding redundant terms avoid glitches(here grouped ones so static 1 hazard)

* Glitches also occur in asynchronous counters due to mismatch in propogation delays


In first image without any additonal circuitry , the pulse will be detected only if the
(Tpulse>=Tclk)
in second image with use of pulse detector we have achieved.

That circuit is

Edge detector:
-----------------------
that detects the short pulses it takes input to posedge trigg clk i/p and produces o/p 1at
posedge
in simple terms ...............it detect posedge of i/p and produce o/p 1
synchroniser :
---------------------
1)synchronises the input

2)reset the egde detector circuit after 2 clock cycles

Oneshot:
---------------
makes o/p 1 for exacly one clock cycle.
*****works only dor synchronous inputs

for example:

here in above xample for asynchronous input output will not be oneshot!!!!!!!

You might also like