Notes - Unit 7

ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY
ECE-2700: Digital Logic Design Fall 2023
Unit 7 – Introduction to Digital System Design

DIGITAL SYSTEM MODEL
▪ FSM + Datapath Circuit:
DATAPATH CIRCUIT
Inputs
FINITE STATE Outputs
resetn
MACHINE
clock
CONTROL CIRCUIT
USE OF GENERIC COMPONENTS

▪ Among the most common components used in the development of digital systems we have registers, shift registers, and
counters. To optimize design time, it is recommended to use parameterized components (VHDL for FPGA Tutorial – Unit 5):
✓ n-bit register with enable and synchronous clear: my_rege
✓ Counter modulo-N with enable and synchronous clear: my_genpulse_sclr
✓ n-bit parallel access (right/left) register with enable and synchronous clear: my_pashiftreg_sclr
EXAMPLES
EXAMPLE: CAR LOT COUNTER
photo If A = 1 → No light received (car obstructing LED A)

receptors If B = 1 → No light received (car obstructing LED B)
If car enters the lot, the following sequence (A|B) must be followed:
B 00 → 10 → 11 → 01 → 00
If car leaves the lot, the following sequence (A|B) must be followed:
00 → 01 → 11 → 10 → 00
A A car might stay in a state for many cycles since the car speed is very large
compared to that of the clock frequency.
DIGITAL SYSTEM (FSM + Datapath circuit)

▪ Usually, when ‘resetn’ (asynchronous clear) and ‘clock’ are not drawn, they are implied.
resetn
A
E E 10
ud Q
B FINITE STATE ud
MACHINE
CONTROL CIRCUIT
clock 10-bit counter
DATAPATH CIRCUIT
1 Instructor: Daniel Llamocca

▪ Finite State Machine (FSM):
A|B/E|ud
00/00 10/00 11/00 01/00
resetn = 0 10/00
11/00 00/00 10/00 11/00

01,10,11/00 S1 S2 S3 S4 S5
00/00 10/00 11/00 01/00

01/00 00/11
00/00
00/00
00/00 01/00
01/00 11/00 10/00
10/00 10/00
01/00 11/00
S6 S7 S8
01/00 11/00
00/10
▪ Algorithmic State Machine (ASM) chart:

resetn=0
S1
no
AB=00
yes
S2
11 00
AB
10 01
S3 S6
00 10 01 00
AB AB
01 11 11 10
S4 S7
10 11 11 01
AB AB
00 01 10 00
S4 S8
00 01 10 00
E, ud  1 AB AB E 1
10 01
11 11

EXAMPLE: ACCUMULATOR

▪ Register: sclr: Synchronous clear. If E = ‘1’ and sclr = ‘1’, then the output bits of the registers are set to zero.
resetn
20
sign
extension
+ D Q Dout
sclr
8 8 20
Din D Q
E
E
Ei
E
sclr
restart FINITE STATE
MACHINE
DATAPATH CIRCUIT
▪ Finite State Machine (FSM):

E|restart/Ei|sclr
resetn = 0 00/00
00/00
10/10
S1 S2
X1/11
10/10
X1/11
▪ Algorithmic State Machine (ASM) Chart:
resetn=0
S1
1
restart Ei, sclr  1
0
E
1
Ei  1
S2
1
Ei, sclr  1 restart
0
E
1
Ei  1

EXAMPLE: 7-SEGMENT SERIALIZER (VHDL CODE)

▪ Most FPGA Development board have a number of 7-segment displays (e.g., 4, 8). However, only one can be used at a time.
▪ If we want to display four digits (inputs A, B, C, D), we can design a serializer that will only show one digit at a time on the
7-segment displays.
▪ Since only one 7-segment display can be used at a time, we need to serialize the four HEX (or BCD) outputs. In order for
each digit to appear bright and continuously illuminated, each digit is illuminated for 1 ms every 4 ms (i.e. a digit is un-
illuminated for 3 ms and illuminated for 1 ms). This is taken care of by feeding the output 𝑧 of the ‘counter to 0.001s’ to the
enable input of the FSM. This way, state transitions only occur each 0.001 s.
▪ Note: the input signals as well as the enable signals to the four 7-segment displays are active low (this is the proper
configuration for the Nexys A7-50T/A7-100T, Nexys 4-DDR).
4
A 0
4
B 1 4 HEX to 7
7
segments
C 4 2 decoder
D 4 3
Counter z
(0.001s)
2-to-4 buf 4 buf(3) buf(2) buf(1) buf(0)

decoder
resetn s
DATAPATH CIRCUIT
E
FINITE STATE MACHINE
▪ Generic Component: Behavior on the clock tick.
0.001 s counter (modulo-105): Free running counter

if Q = 105 - 1 then
Q  0 resetn=0
else S1
Q  Q+1 s  00
end if;
end if;
0
E
* z = 1 if Q = 105-1
1
S2
▪ Algorithmic State Machine (ASM) chart: This is a Moore-type FSM. s  01
0
E
1
S3
s  10
0
E
1
S4
s  11
1 0
E

EXAMPLE: BIT-COUNTING CIRCUIT (Parametric VHDL Code) (Video: VHDL coding in Vivado, n=8)
▪ It counts the number of bits in a register A that have the value ‘1’. SEQUENTIAL ALGORITHM
▪ Example: A=10110011 → count = 0101.
C  0
DIGITAL SYSTEM (FSM + Datapath circuit) while A  0
▪ FSM: as a ASM Chart. Modulo-n+1 bit counter (m bits): it has synchronous clear (𝑠𝑐𝑙𝑟). if a0 = 1 then
▪ Generic components: Behavior on the clock tick: C  C + 1
end if
Counter modulo-n+1 (0 to n): n-bit Parallel access shift register:
right shift A
If E=0, the count stays. If E=0, the output is kept end while
if E = 1 then if E = 1 then
if sclr = 1 then if s_l = ‘1’ then
Q  0 Q  D
elseif Q = n then else
Q  0 Q  shift in ‘din’ (to the right)
else end if;
Q  Q+1 end if;
end if;
end if; DA resetn=0
resetn S1
𝑛 EC, sclrC  1
0 din 0
LA s_l s
EA E A
𝑚 C
1
EC
E Q
Parallel Access 𝑛 Shift-Right EA, LA  1
sclrC
Right Shift (MSB to LSB) sclr
s_l = 1 → Load S2
s_l = 0 → Shift
counter: m bits
𝑚= 𝑛
LA EA 1
z
0
EA  1
z a0
DATAPATH CIRCUIT S3
done  1 0
a0
FINITE STATE
MACHINE done 1
s 0 1
s
EC  1
▪ Example (timing diagram): 𝑛 = 8, 𝑚 = 4. Video: Timing diagram completion (different DA values)
clock
resetn
DA 00110110 00001110
A 00 00 36 1B 0D 06 03 01 00 00 00 0E 07 03 01 00 00
state S1 S1 S2 S2 S2 S2 S2 S2 S2 S3 S1 S2 S2 S2 S2 S2 S3
C 0000 0000 0000 0000 0001 0010 0010 0011 0100 0100 0100 0000 0000 0001 0010 0011 0011
sclrC
EC
done
EA
LA
EXAMPLE: SEQUENTIAL MULTIPLIER (Parametric VHDL Code) (Video: VHDL coding in Vivado, n=4)
UNSIGNED MULTIPLICATION: SEQUENTIAL ALGORITHM
Example: 1 1 1 1 x
1 1 0 1
P  0, Load A,B
1 1 1 1 P  0 + 1111
while B  0
0 0 0 0 P  1111
if b0 = 1 then
1 1 1 1
P  P + A P  1111 + 111100 = 1001011
1 1 1 1
end if P  1001011 + 1111000 = 11000011
left shift A 1 1 0 0 0 0 1 1
right shift B P  0, A  1111, B  1101
end while b0=1  P  P + A = 1111. A  11110, B  110
b0=0  P  P = 1111. A  111100, B  11
b0=1  P  P + A = 1111 + 111100 = 1001011. A  1111000, B  1
b0=1  P  P + A = 1001011 + 1111000 = 11000011. A  11110000, B  0

▪ Iterative Multiplier Architecture. Register P: 𝑠𝑐𝑙𝑟: synchronous clear. The result is computed in at most 𝑛 cycles.
𝑛 𝑛 DataB
DataA 00..0
𝑛 "00..0"&DataA 𝑛
resetn
0 din 0 din
L s_l L s_l
E E A E E B
sclrP
𝑛 Shift-left 𝑛 Shift-right
EP
E
L
s z +
FSM 𝑛
b0
EP E z b0
sclrP sclr P
done 𝑛
DATAPATH CIRCUIT
▪ Generic Components: Behavior on the clock tick: P

2n-bit register: Parallel access shift register: If E=0, the output is kept
resetn=0
If E=0, the output is kept A (2n bits, left shift), B (n bits, right shift) S1
if E = 1 then if E = 1 then sclrP  1
if sclr = 1 then if s_l = ‘1’ then EP  1
Q  0 Q  D
else else
Q  D Q  shift in ‘din’ s
0
end if; (to the left(A) or right(B))
end if; end if; 1
end if; L, E  1
▪ Algorithmic State Machine (ASM) chart  S2

E1
1 0
z
S3 0
done  1 b0
1
0 1
s EP  1

▪ Timing Diagram example: 𝑛 = 4
clock
resetn
DA 1111 1111
DB 1111 1101
A 00 00 0F 1E 3C 78 F0 E0 E0 E0 0F 1E 3C 78 F0 E0 E0
B 0000 0000 1111 0111 0011 0001 0000 0000 0000 0000 1101 0110 0011 0001 0000 0000 0000
state S1 S1 S2 S2 S2 S2 S2 S3 S1 S1 S2 S2 S2 S2 S2 S3 S1
P 00 00 00 0F 2D 69 E1 E1 E1 00 00 0F 0F 4B C3 C3 C3
done
sclrP
EP
EXAMPLE: RGB LED CONTROL

▪ We change the color of the RGB LED every 0.5 seconds. Two modes are allowed (based on an input ‘x’).
✓ First Mode: BLACK → RED → GREEN → BLUE resetn=0
✓ Second Mode: BLACK → YELLOW → CYAN → VIOLET S1
RGB  000
0
E
R G B R G B 0 1
x
0 0 0 0 0 0
1 0 0 1 1 0
x=0 x=1 S2a S2b
0 1 0 0 1 1
RGB  100 RGB  110
0 0 1 1 0 1
0 0
E E
resetn 1 1
S3a S3b
RGB  010 RGB  011
'1' E Counter
(0.5s) z
0 0
E E
DATAPATH CIRCUIT 1 1
S4a S4b
E R RGB  001 RGB  101
x FINITE STATE G
MACHINE B
1 0 0 1
E E

EXAMPLE: CAN BIT STUFFING (RECEIVER)

▪ Whenever a CAN transmitter detects 5 consecutive identical bits, it inserts a complemented bit. This is applied only to the
start-of-frame field, arbitration, control, data, and CRC field. The figure shows a frame in the CAN version 2.0b.
Arbitration Field Control Field CRC field
Standard
DLC3
DLC2
DLC1
DLC0
RTR
IDE
11-bit identifier CRC sequence (15 bits) 1
r0
Format:
Data Length Code

CRC delimiter
12 (standard) Interframe
1 6 0-64 16 2 7
32 (extended) Space
Start of Start of
Arbitration Field Control Field Data Field Data Field CRC Field ACK End of Frame
Frame Frame
Recessive bits
Arbitration Field Control Field ACK field
Extended
DLC3
DLC2
DLC1
DLC0
ACK
SRR
RTR
IDE
slot
11-bit base identifier 18-bit extended identifier 1
r1
r0
Format:
Data Length Code

▪ In a CAN receiver, we have to verify whether the stuffed bits are correct: ACK delimiter
recessiv e from sender
1 0 0 0 0 0 1 1 1 1 1 1 0
changed into dominant for ack
t
Stuffed bits
DIGITAL SYSTEM (FSM + Datapath Circuit) resetn=0
▪ Input signal 𝑥: qualified by S1
can_destuff
EC  1
𝐸. The system generates x x_d sclrC  1
𝑥_𝑑 (de-stuffed 𝑥) qualified E
by v. If 6 consecutive bits xq counter
Ex 0
are identical, we assert 0 to 3 E
EC 2
stuff_err (stuffing error). E Q 1
E sclrC
▪ We compare two FSM sclr
consecutive samples (𝑥[𝑛] z zC Ex  1, v d  1

resetn err vd
and 𝑥[𝑛 − ]). Here, 𝑥 = v S2
𝑥[𝑛] and 𝑥_𝑑 = 𝑥[𝑛 − ]. clock zC
stuff_err
To determine whether 5
consecutive bits are identical, we compare 𝑥[𝑛] and 𝑥[𝑛 − ] four times.
▪ Finite State Machine: E 0
✓ S1: captures the first bit, though there is no other bit to compare it to.
1
✓ S2: captures the other incoming bits, and it compares two consecutive bits at a
time. If they match, then CC+1, otherwise C0. This can happen indefinitely Ex  1, v d  1
until C=3 and these two bits match (i.e., after 4 comparisons, we determined that
5 consecutive bits are identical). Then, we move to S3. no EC  1
✓ S3: It determines whether the stuffed bit is correct. If the 5th and 6th bits match, x=xq slcrC  1
there is an error. On the next cycle, 𝑥_𝑑 is invalid and we do not assert the valid y es
flag v, as we are de-stuffing this extra bit. We then return to S1 and start over.
▪ In the figure, we start right after resetn was asserted. Cases: 111111, 000001. E=1. zC
0
EC  1
1
clock S3
x
0
x_d E
state S1 S2 S2 S2 S2 S3 S1 S2 S2 S2 S2 S3 S1 1
no
C 0 0 1 2 3 3 3 0 1 2 3 3 3 x=xq
y es
v
err  1
stuff_err

EXAMPLE: SERIAL DATA TRANSMISSION WITH UART (VHDL CODE)
UART Interface
▪ This interface transfers data asynchronously (clock is not FT2232 Artix-7 - Nexys4
transmitted; transmitter and receiver use their own clocks). Micro
TXD
▪ Data communication: RXD (receive pin), TXD (transmit pin). The USB C4 (RXD)
FT2232 chip inside the Nexys-4 board is in charge of handling
RXD D4 (TXD)
the USB communication with a computer.
▪ Format of a Frame: Start bit (‘0’), 8 to 9 data bits (LSB
transmitted first), optional parity bit, and a stop bit (‘1’).
▪ Transmitter: Simple design that transmit the data frame at the Baud rate (or bit rate in bps).
▪ Receiver: It uses a clock signal whose frequency is a multiple (usually 16) of the incoming data rate.
Baud rate clock
TXD start DO D1 D2 D3 D4 D5 D6 D7 stop
DIGITAL SYSTEM (FSM + Datapath circuit) resetn=0

▪ This circuit sends data from the Artix-7 FPGA (that is read via S1
switches) to the FT2232 chip. TXD  1
▪ For a baud rate of 9600 bps, the Baud rate clock is 9600 Hz. The bit
time is 104.2 us. 1
1⁄ E
Then: 𝑁 = 9600
= 04 6. We need a counter modulo-𝑁 in order
10 𝑛𝑠 0
to generate the proper time interval (bit time of 104.2 us). S2
TXD  1
▪ Generic component (counter): Behavior on the clock tick:
If E=0, the count stays.
if E = 1 then 0
E
if sclr = 1 then
Q  0 1
else
Q  Q+1 LR, ER  1
end if;
S3
end if;
* z=1 if Q = N-1 (max. count) TXD  0
✓ Note that the way this counter (my_genpulse_sclr) is designed, 0

zC EC  1 (C C+1)
once the maximum count is reachd, asserting enable to ‘1’ will START bit
set the count to 0. 1
E TXD SW If max count is reached,
EC  1 (C 0)
EC=1 makes C=0
8
S4
so
EC dout TXD  so
EQ LR s_L RIGHT SHIFT
FSM ER 0
E REGISTER din
0
zC EC  1 (C  C+1) 8 DATA bits
8
zC zQ 1
EQ EC
resetn E Q 3 E Q n EC  1 (C 0), ER  1
0 sclr 0 sclr
clock zQ zC
z z 0
zQ EQ  1 (Q  Q+1)
counter counter
0 to 7 0 to N-1 1
If max count is reached,

EQ  1 (Q 0)
EQ=1 makes Q=0
S5
TXD  1
STOP bit
1 0
EC  1 (C 0) zC EC  1 (C C+1)

EXAMPLE: PS/2 INTERFACE FOR KEYBOARD (VHDL CODE)
PS/2 Interface
▪ This interface transfers data synchronously (clock is transmitted PIC24FJ128 Artix-7 - Nexys4
alongside data).
▪ The PIC24FJ128 chip (auxiliary function microcontroller) inside the
Connector
USB Host
Nexys-4 DDR board emulates an old-style PS/2 bus and presents a
PS/2 protocol to the FPGA. The PS/2 bus signals are converted to the PS2_CLK F4
USB protocol. Thus, we can interface with a USB keyboard or mouse
PS2_DAT
as if they were using the PS/2 protocol. B2
▪ PS/2 bus uses a bidirectional two-wire serial bus (PS2_CLK and
PS2_DATA) to communicate with a host. The FPGA plays the role of the host.
▪ Format of a Frame: Start bit (‘0’), 8 data bits (LSB transmitted first), parity bit (odd), and a stop bit (‘1’).
▪ Timing Diagram: Data (1 byte) is captured on the falling edge. The following are times found in the Nexys-4 DDR datasheet:
T  [60 us,100 us], tSU, tHD  [5 us,25 us]
PS2_CLK
PS2_DAT start DO D1 D2 D3 D4 D5 D6 D7 p stop
T tSU tHD
BYTE READ - DIGITAL SYSTEM (FSM + Datapath) my_ps2read

▪ This system can only receive data from the
ps2d
PIC24FJ128. Thus, it only reads the PS2_CLK and din
0 s_L RIGHT SHIFT
PS2_DAT signals. ps2c filter REGISTER dout
E
▪ 10-bit output: |STOP|parity|D7-D0|. ps2cf
falling edge
▪ Counter: EQ=1  Q  Q+1. Note that once the detector 10
maximum count is reached, asserting enable to ‘1’ FSM DOUT
resets the count to 0. EQ
E Q
4
▪ Falling Edge Detector. This FSM detects transitions resetn FSM
from 1 to 0 on ps2cf. fall_edge MAIN zQ
clock counter
0 to 9
zQ done_d
done
Falling Edge Detector FSM MAIN

resetn=0 resetn=0
S1 S1
clock
resetn
0 0
ps2cf fall_edge
START bit
1 ps2cf 1
S2
1
fall_edge ps2d
0
1 S2
ps2cf
0
+ Parity + STOP bit
f all_edge  1 0
8 DATA bits
fall_edge
E, EQ  1
done_d  1
1 0
zQ

▪ Filter: It makes sure that ps2c (PS2_CLK) is constant for at least 8 clock cycles (FPGA operating frequency) before ps2cf
is assigned a ‘1’ or a ‘0’. This mitigates the presency of glitches that may have been interpreted as falling edges. The choice
of 8 cycles is based on actual testing (use more cycles if you notice glitches affecting the functioning of the circuit.
Filter
ps2c din
0 s_L RIGHT SHIFT clock
1 E REGISTER
8 ps2c
ps2cf
all 1's? all 0's?
a b DE a b
0 0 X0 D ps2cf
0 1 01 E
1 0 11
1 1 01
INTERFACING WITH A PS/2 KEYBOARD

▪ Data from the PS/2 keyboard is given as an 8-bit scan code (see Nexys4-DDR datasheet for a list of scan codes). The
following is the protocol that is used when a key is pressed:
✓ If a key is held, the scan code is sent repeatedly every 100 ms.
✓ When the key is released, an F0 key-up code is sent, followed by the scan code of the released key.
✓ If a key can be shifted to produce a new character (like a capital letter), then a shift character is sent alongside the scan
code. Example: F0 12 [scan code].
✓ Some keys, called extended keys, send an E0 ahead of the scan code. When an extended key is released, an E0 F0
key-up code is sent, followed by the scan code.
▪ The circuit presented here cannot read extended keys or shifted keys, only normal keys. It waits for the key-up code (F0),
and then it captures the scan code. For example, for ‘U’, the PS/2 keyboard sends |F0|3C|, this circuit retrieves 3C.
▪ The block my_ps2read outputs 10 bits when it receives any code from the PS/2 keyboard. Example:
 000000 =
✓ DOUT10 = 1111000000, where parity bit is ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
✓ DOUT10 = 1100111100, where parity bit is 00    00 =
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
✓ DOUT10 = 1100011100, where parity bit is 000   00 = 0
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
▪ The timing diagram shows when the ‘U’ key is pressed and released: F0 (key-up code) is sent first, then 3C (scan code).
resetn=0
my_ps2keyboard S1
ps2d 10 8 8
D Q DOUT
my_ps2read DOUT10 E
ps2c 0
8 Er done_r
done_r
DOUT8 done
1
no
FSM dout8=F0
resetn KEY-UP
CODE
y es
clock
S2
done_r 0
SCAN
1
CODE
Er  1
clock
done_r
DOUT10 3F0 33C
DOUT8 F0 3C
DOUT 3C
done

EXAMPLE: ARTIFICIAL NEURON

▪ Artificial neuron model. The membrane potential 𝒛 is a sum of products membrane action
(input activations 𝑎𝑖 by weights 𝑤𝑖 ) to which a bias term 𝑏 is added. The potential potential
action potential 𝒂𝒐 is modeled as a scalar function of 𝒛. The figure depicts a
neuron with 5 inputs. The bias and the weights are constant values.
𝑎𝑜 = 𝜎 (∑ 𝑎𝑖 × 𝑤𝑖
𝑖
𝑏)
S
✓ A popular and simple scalar function is the Rectified Linear Unit (ReLU):
 𝜎(𝑧) = 𝑧 if 𝑧 ≥ 0, otherwise 𝜎(𝑧) = 0.
▪ DIGITAL SYSTEM (FSM + Datapath): An iterative architecture for a 5-input

neuron is depicted. The circuit captures the input data (𝑎1 , 𝑎 , 𝑎3 , 𝑎4 , 𝑎5 ) and then computes 𝒛 using a multiply-and-
accumulate approach (see iterative algorithm). The output 𝒂𝒐 is computed by applying the ReLU function to 𝒛.
✓ All data is represented as signed integers:

 Input activations (𝑎1 , 𝑎 , 𝑎3 , 𝑎4 , 𝑎5 ), weights (𝑤1 , 𝑤 , 𝑤3 , 𝑤4 , 𝑤5 ), bias (𝑏): 4-bits wide.
 Weights and biases: They are constant values.
 Membrane potential (𝒛) and action potential (𝒂𝒐): 12-bits wide (11 bits suffice, we select 12 for simplicity’s sake).
✓ Example (this is what appears in the timing diagram, where 𝒛 and 𝒂𝒐 are in hexadecimal format):
 𝑤1 = 04, 𝑤 = 0 , 𝑤3 = 0 , 𝑤4 = 08, 𝑤5 = 0 . 𝑏 = 06
 If 𝑎1 = 04, 𝑎 = 0𝐸, 𝑎3 = 0𝐶, 𝑎4 = 05, 𝑎5 = 0𝐴.
 Then 𝒛 = 44 −  −4 5(−8) −6 = −40 = 0𝐹𝐷8. Finally, 𝒂𝒐 = 0000
✓ Components:
 Counter 0 to 4: If E=1, sclr=1, then Q  0. If E=1, sclr=0, then Q  Q+1. Also: z=1 if Q = 4, else z=0.
 Register: If E=1, sclr=1→ Clear. If E=1, sclr=0 → Load data.
 44 Signed Multiplier: Combinational circuit, whose result is 8-bits wide (sign-extended to 12 bits).
 ReLU: Combinational Block that implements the ReLU operation. For example, if 𝒛 = 0𝐹𝐷8, then 𝒂𝒐 = 0000
✓ FSM: The process begins when s is asserted, at this moment we capture 𝑎1 , 𝑎 , 𝑎3 , 𝑎4 , 𝑎5 on the input registers. Then 𝒛
is updated until the counter reaches its maximum value (4). The signal done is asserted when the final result is computed.
4 4 4 4 4 4
0 1 2 3 4
4
E 0
4
4
1
E
4 4 ALGORITHM
2
E sign extension
4 8
3 to 12 bits
E
4
4
E
0 1 sb
12 12
3
i +
12
E
sclr
resetn
sclro
sclri
Ei
Eo
E 3
Ei
clock E Q i
12 sclri sclr
z zi
sb
s FSM Counter
zi ReLU
0 to 4
12
done
FSM:
clock
resetn=0
resetn S1
Ei, sclri  1
0x4EC5A
0
s s
state S1 S1 S2 S2 S2 S2 S2 S3 S4 S1 1
E, Eo, sclro  1
i 000 000 000 001 010 011 100 000 000 000
S2
E Eo  1
sclri 0
zi Ei  1
Ei i=4? 1
sb Ei, sclri  1
S3
sclro sb  1, Eo  1
Eo S4
done  1
000 000 000 010 00E 006 FDE FD2 FD8 FD8
0 1
000 000 000 010 00E 006 000 000 000 000 s
done

EXAMPLE: SIMPLE PROCESSOR

▪ This system is a basic Central Processing Unit (CPU). For completeness, a memory would need to be included.
SWITCHES
LEDS
E
IN
E
OUT
4
0
4 4
1 BUS
4
2
4
3 E E E
R1 R0 A B
2
ALU
E_OUT
E_IN
E_R1
E_R0
E_A
SM
op
E
G
4
E_G
w
IR
5 done
CONTROL CIRCUIT
▪ Instruction Set
Every time w=1, we grab the instruction from IR and execute it.
Instruction = |f2|f1|f0|Ry|Rx|. This is called ‘machine language instruction’ or Assembly instruction.
✓ Opcode (operation code): IR(4..2). These bits specify the operation to be performed.
✓ Operands: IR(1..0). These bits specify the register indices to be used in the operation:
 Rx: index of the register where the result of an operation is stored (we also read data from Rx). Rx can be R0 or R1.
 Ry: index of the register where we only read operands from. Ry can be R0 or R1.
f (IR[4..2]) Operation Function

000 load IN IN  Switches
001 load Rx, IN Rx  IN
010 copy Rx, Ry Rx  Ry
011 add Rx, Ry Rx  Rx + Ry
100 add Rx, IN Rx  Rx + IN
101 xor Rx, Ry Rx  Rx XOR Ry
110 inc Rx Rx  Rx + 1
111 load OUT, Rx OUT  Rx

▪ Control Circuit:
E_OUT
Here, the Control Circuit could be implemented as
E_IN
E_A
E_G
SM
op
an FSM. However, in order to simplify the FSM
design, the Control Circuit was built out of some CONTROL
combinational units, a register, and an FSM. The CIRCUIT 2 4
5-bit instruction is captured on the signal IRq.
w
3 done
✓ Ex: Every time we want to enable register 𝑅𝑥, f FSM
the FSM only asserts Ex (instead of controlling
E_R0, E_R1 directly). The decoder takes care
of generating the enable signal for the
E_IR Ex Rx Ry
corresponding register 𝑅𝑥. Rx w DECODER 0
5 5 E_R0
IR D Q IRq with
Ex E enable 1 E_R1
E
opcode
E_IR
IRq = |f2|f1|f0|Ry|Rx|
✓ Control Circuit: FSM

resetn=0
S1
0
w
1
E_IR  1
S2
000 111
E_IN  1 f
110
001
SM  00, Ex  1
010
011 100 101
SM  1&Ry , SM  1&Rx SM  1&Rx SM  1&Rx SM  1&Rx, SM  1&Rx,

Ex  1 E_A  1 E_A  1 E_A  1 op  0100 E_OUT  1
E_G  1
S3a S4a S5a

S6
SM  1&Ry , SM  00, SM  1&Ry ,
E_G  1 E_G  1 E_G  1 SM  01
op  0110 op  0110 op  1110 Ex  1
S3b S4b S5b

SM  01, SM  01 SM  01,
Ex  1 Ex  1 Ex  1
S7
done  1
0 1
w

▪ Arithmetic Logic Unit (ALU):
op Operation Function Unit

0000 y <= A Transfer ‘A’
0001 y <= A + 1 Increment ‘A’
0010 y <= A - 1 Decrement ‘A’
0011 y <= B Transfer ‘B’
0100 y <= B + 1 Increment ‘B’ Arithmetic
0101 y <= B – 1 Decrement ‘B’
0110 y <= A + B Add ‘A’ and ‘B’
0111 y <= A – B Subtract ‘B’ from 'A'
1000 y <= not A Complement ‘A’
1001 y <= not B Complement ‘B’
1010 y <= A AND B AND
1011 y <= A OR B OR
1100 y <= A NAND B NAND Logic
1101 y <= A NOR B NOR
1110 y <= A XOR B XOR
1111 y <= A XNOR B XNOR
▪ Assembly code example:
load IN; IN  0101 (SWs = 0101)

load R1, IN; R1  0101
copy R0, R1; R0  0101, R1  0101
inc R1; R1  0110
xor R0, R1; R0  0101 xor 0110 = 0011
add R0, R1; R0  0011 + 0110 = 1001
load OUT, R0; OUT  1001

EXAMPLE: SIMPLE PROCESSOR WITH 3-STATE BUFFERS
n n
Data_in D Q
Data
BUS
E E E E E
R0 R1 R2 R3 A B
ALU
E_R2
O_R2
E_R3
O_R3
E_R0
O_R0
E_R1
O_R1
E_A
op
E
G
E_ext
4
E_G
O_G
w
done
7 CONTROL CIRCUIT
fun
▪ Instruction Set
Every time w = '1', we grab the instruction from 𝑓𝑢𝑛 and execute it.
𝐼𝑛𝑠𝑡𝑟𝑢𝑐𝑡𝑖𝑜𝑛 = |𝑓 |𝑓1 |𝑓0 |𝑅𝑦1 |𝑅𝑦0 |𝑅𝑥1 |𝑅𝑥0 |. This is called ‘machine language instruction’ or Assembly instruction:
✓ 𝑓 𝑓1 𝑓0 : Opcode (operation code). This is the portion that specifies the operation to be performed.
✓ 𝑅𝑥: Register where the result of the operation is stored (we also read data from 𝑅𝑥). 𝑅𝑥 can be R1, R2, R3, R4.
✓ 𝑅𝑦: Register where we only read data from. 𝑅𝑦 can be R1, R2, R3, R4.
f Operation Function
000 Load Rx, Data Rx  Data
001 Move Rx, Ry Rx  Ry
010 Add Rx, Ry Rx  Rx + Ry
011 Sub Rx, Ry Rx  Rx - Ry
100 Not Rx Rx  NOT (Rx)
101 And Rx, Ry Rx  Rx AND Ry
110 Or Rx, Ry Rx  Rx OR Ry
111 Xor Rx, Ry Rx  Rx XOR Ry

▪ Control Circuit:
This is made out of some combinational units, a register, and a FSM:
✓ Ex: Every time we want to enable register 𝑅𝑥, the FSM only asserts Ex (instead of controlling E_R0, E_R1, E_R2, E_R3
directly). The decoder takes care of generating the enable signal for the corresponding register 𝑅𝑥.
✓ Eo, so: Every time we want to read from register 𝑅𝑦 (or 𝑅𝑥), the FSM only asserts Eo (instead of controlling O_R0,
O_R1, O_R2, O_R3 directly) and so (which signals whether to read from 𝑅𝑥 or 𝑅𝑦). The decoder takes care of generating
the enable signal for the corresponding register 𝑅𝑥 or 𝑅𝑦.
7 7 Rx1 0 0
fun D Q funq DECODER 1 E_R0
Rx0 E_R1
E_fun E 1 with 2 E_R2
enable 3 E_R3
Ex
E
Ry 2 0 0 0
2 O_R0
2 DECODER 1
Rx 1 O_R1
1 with 2 O_R2
enable 3 O_R3
Eo
E
so
funq = |f2|f1|f0|Ry1|Ry 0|Rx1|Rx0|

E_fun
E_ext
O_G
E_G
E_A
op
Ex Eo so
4
w
3 done
f FSM
▪ Arithmetic-Logic Unit (ALU):
op Operation Function Unit

0000 y <= A Transfer ‘A’
0001 y <= A + 1 Increment ‘A’
0010 y <= A - 1 Decrement ‘A’
0011 y <= B Transfer ‘B’
0100 y <= B + 1 Increment ‘B’ Arithmetic
0101 y <= B – 1 Decrement ‘B’
0110 y <= A + B Add ‘A’ and ‘B’
0111 y <= A – B Subtract ‘B’ from 'A'
1000 y <= not A Complement ‘A’
1001 y <= not B Complement ‘B’
1010 y <= A AND B AND
1011 y <= A OR B OR
1100 y <= A NAND B NAND Logic
1101 y <= A NOR B NOR
1110 y <= A XOR B XOR
1111 y <= A XNOR B XNOR

▪ Algorithmic State Machine (ASM) Chart:

Every branch of the FSM implements an Assembly instruction.
resetn=0
S1
0
w
1
E_fun  1
S2
E_ext, Ex  1 000 111

f
done  1
110
001
Eo, Ex  1
done  1 010
011 100 101
Eo, so  1 Eo, so  1 Eo, so  1 Eo, so  1 Eo, so  1 Eo, so  1

E_A  1 E_A  1 E_A  1 E_A  1 E_A  1 E_A  1
S3a S4a S5a S6a S7a S8a

Eo, E_G  1 Eo, E_G  1 E_G  1 Eo, E_G  1 Eo, E_G  1 Eo, E_G  1
op  0110 op  0111 op  1000 op  1010 op  1011 op  1110
S3b S4b S5b S6b S7b S8b

O_G, Ex  1 O_G, Ex  1 O_G, Ex  1 O_G, Ex  1 O_G, Ex  1 O_G, Ex  1
done  1 done  1 done  1 done  1 done  1 done  1

EXAMPLE: DISPLAYING PATTERNS ON 7-SEGMENT DISPLAYS

▪ Different patterns are shown based on the selector ‘sel’ signal. Two 7-segment displays are used.
▪ ‘stop’ input: If it is asserted (stop = 1), the lights’ pattern freezes.
▪ The input ‘x’ selects the rate of change (every 1.5, 1.0, 0.5, or 0.25 seconds).
segs[7..0] : sel 2
8 segs
7 6
x 2
0
1
5
4
stop
resetn
?
2 3 clock
sel[1..0]
00
01
10
11

x stop sel
resetn
clock
Q ?? 2 2
On the NEXYS4, only one 7-segment
7 display can be used at a time
z dseg 0
0
8 8 7
counter (1.5s) D Q
E FINITE STATE
1 MACHINE Esg
E 7
1
Q ?? 2
3
z
counter (1.0s) Counter z

(0.001s)
E
Q ?? FINITE STATE 1-to-2 buf buf(1) buf(0)
MACHINE s decoder
z
counter (0.5s) x = 00 → Lights change every 1.5 s
x = 01 → Lights change every 1.0 s
Q ??
counter (0.25s)

▪ Algorithmic State Machine (ASM) chart:

resetn=0
S1
0
E
1
00 11
sel
01 10
dseg00000111, Esg1 dseg00000101, Esg1 dseg00000011, Esg1 dseg00110011, Esg1
S2 S5 S8 S11
0 0 0 0
E E E E
1 1 1 1
S3 S6 S9 S12
0 0 0 0
E E E E
1 1 1 1
S4 S7 S10 S13
0 0 0 0
E E E E
1 1 1 1
▪ Algorithmic State Machine (ASM) chart: This is the FSM that controls the output MUX
resetn=0
S1
s0
0
E
1
S2
s1
1 0
E

Notes - Unit 7

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Notes - Unit 7

Uploaded by

Copyright:

Available Formats

ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY

ECE-2700: Digital Logic Design Fall 2023

Unit 7 – Introduction to Digital System Design

USE OF GENERIC COMPONENTS

photo If A = 1 → No light received (car obstructing LED A)

DIGITAL SYSTEM (FSM + Datapath circuit)

1 Instructor: Daniel Llamocca

▪ Finite State Machine (FSM):

11/00 00/00 10/00 11/00

00/00 10/00 11/00 01/00

▪ Algorithmic State Machine (ASM) chart:

2 Instructor: Daniel Llamocca

DIGITAL SYSTEM (FSM + Datapath circuit)

▪ Finite State Machine (FSM):

3 Instructor: Daniel Llamocca

EXAMPLE: 7-SEGMENT SERIALIZER (VHDL CODE)

DIGITAL SYSTEM (FSM + Datapath circuit)

2-to-4 buf 4 buf(3) buf(2) buf(1) buf(0)

FINITE STATE MACHINE

▪ Generic Component: Behavior on the clock tick.

0.001 s counter (modulo-105): Free running counter

4 Instructor: Daniel Llamocca

▪ Example (timing diagram): 𝑛 = 8, 𝑚 = 4. Video: Timing diagram completion (different DA values)

UNSIGNED MULTIPLICATION: SEQUENTIAL ALGORITHM

DIGITAL SYSTEM (FSM + Datapath circuit)

▪ Generic Components: Behavior on the clock tick: P

▪ Algorithmic State Machine (ASM) chart  S2

6 Instructor: Daniel Llamocca

▪ Timing Diagram example: 𝑛 = 4

EXAMPLE: RGB LED CONTROL

7 Instructor: Daniel Llamocca

EXAMPLE: CAN BIT STUFFING (RECEIVER)

Data Length Code

Arbitration Field Control Field ACK field

Data Length Code

consecutive samples (𝑥[𝑛] z zC Ex  1, v d  1

8 Instructor: Daniel Llamocca

EXAMPLE: SERIAL DATA TRANSMISSION WITH UART (VHDL CODE)

Baud rate clock

TXD start DO D1 D2 D3 D4 D5 D6 D7 stop

DIGITAL SYSTEM (FSM + Datapath circuit) resetn=0

✓ Note that the way this counter (my_genpulse_sclr) is designed, 0

If max count is reached,

9 Instructor: Daniel Llamocca

EXAMPLE: PS/2 INTERFACE FOR KEYBOARD (VHDL CODE)

PS2_DAT start DO D1 D2 D3 D4 D5 D6 D7 p stop

BYTE READ - DIGITAL SYSTEM (FSM + Datapath) my_ps2read

Falling Edge Detector FSM MAIN

10 Instructor: Daniel Llamocca

INTERFACING WITH A PS/2 KEYBOARD

DOUT10 3F0 33C

11 Instructor: Daniel Llamocca

EXAMPLE: ARTIFICIAL NEURON

▪ DIGITAL SYSTEM (FSM + Datapath): An iterative architecture for a 5-input

✓ All data is represented as signed integers:

13 Instructor: Daniel Llamocca

EXAMPLE: SIMPLE PROCESSOR

DIGITAL SYSTEM (FSM + Datapath circuit)

f (IR[4..2]) Operation Function

14 Instructor: Daniel Llamocca

✓ Control Circuit: FSM

SM  1&Ry , SM  1&Rx SM  1&Rx SM  1&Rx SM  1&Rx, SM  1&Rx,