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• Two control bits, IDL and PD, which are used for Idle and
power-down mode respectively.
• In Power Down mode, the oscillator clock provided to the
system is OFF i.e. CPU and peripherals clock remains inactive
in this mode.
• In Idle Mode, only the clock provided to the CPU gets
deactivated, whereas the peripherals clock will remain active
in this mode.
• Hence power saved in power-down mode is more than in idle
mode
Power supply current required for 8051 family
controllers in Normal (Active), Idle and Power-down
modes
Get out from power saving modes
• To Get out from idle mode:
1. By interrupt
This is similar to sleep mode in computers , when the keyboard
key is pressed or the mouse is moved. In this way recent data is
restored.
2. Restart
In this method, the system is restarted, and the previous data is
lost.
• To Get out from power-down mode:
Restart
In this method, the system is restarted, and the previous
data is lost.
Interrupt registers
Reset
• A reset can be considered to be the ultimate
interrupt because the program may not block
the action of the voltage on the RST pin.
• This type of interrupt is often called “non-
maskable,” since no combination of bits in any
register can stop, or mask the reset action.
Internal registers values after Reset
Interrupt Priority
• Register IP bits determine if any interrupt is to have a high or low priority.
• Bits set to 1 give the accompanying interrupt a high priority while a 0
assigns a low priority. Interrupts with a high priority can interrupt another
interrupt with a lower priority; the low priority interrupt continues after the
higher is finished.
• If two interrupts with the same priority occur at the same time, then they
have the following ranking:
1. IE0
2. TF0
3. IE1
4. TF1
5. Serial - RI OR TI
The serial interrupt could be given the highest priority by setting the PS bit
in IP to 1 , and all others to 0.
Interrupt Destinations