ST.

JOSEPH COLLEGE OF ENGINEERING

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

1
EE8551 - MICROPROCESSORS AND
MICROCONTROLLERS

LECTURE – 9
24.08.2020

Presented by
J.Jayashree AP/EEE
SJCE
 UNIT – 1 8085 PROCESSOR
Timing Diagram
Timing Diagram for Operand Fetch (Machine Read) Cycle:
• The 8085 uses this cycle to fetch the operand of an
instruction, if it is a Multi- byte instruction, to read the data
from memory.
• This operations has 3 T- states , i.e.,., T1 to T3 .
• The various states involved during this cycle are:
Step 1(T1 – state)
• In this T1 – state 8085 sends appropriate status signals
, S0, S1.
i.e., = 0, S0 = 0, S1 = 1 (Memory Read).
• The 16-bit address is transferred on A8-A15 and AD0-AD7 .
 UNIT – 1 8085 PROCESSOR
Timing Diagram
• The address us given by the Program Counter.
• ALE is generated by 8085 to latch A0-A7.
Step-2 (T2 – State):
• In T2 state, the content of AD0-AD7 which contains
address A0-A7 are removed but the content of A0-A7
is still available in the memory as latch.
• The lines AD0-AD7 will be used as D0- D7 to transfer
data.
• The control signal RD is made low to enable the
memory selected.
 UNIT – 1 8085 PROCESSOR
Timing Diagram
Step : 3 (Wait State)
• If the IO devices are not synchronised with the
speed of the microprocessor ., ie., the IO devices are
slower, then the microprocessor will insert one or
mare wait states between T2 and T3 states.
• These wait states are optional.
Step : 4 (T3 State)
• In this T-State data from memory is transferred to
8085.
• 8085 accepts this data and transfers on internal data
bus .
 UNIT – 1 8085 PROCESSOR
Timing Diagram
• is made high.
• The location of the result data depends on the
instruction for which this machine cycle is used.
• The result data is stored in the General Purpose
registers.
UNIT – 1 8085 PROCESSOR
Timing Diagram
 UNIT – 1 8085 PROCESSOR
Timing Diagram
• Memory Write Cycle:
The 8085 uses this operation to store data in memory
location.
It requires 3T states. i.e.,., T1 to T3
Step- 1 (T1 – State):
UNIT – 1 8085 PROCESSOR
Timing Diagram
UNIT – 1 8085 PROCESSOR
Timing Diagram
 UNIT – 1 8085 PROCESSOR
Timing Diagram
IO Read Cycle:
• The microprocessor executes these cycles, to read data
from IO devices , instead of , memory.
• The address of the port is given by the instructions.
• The time required to complete the cycle is 3T states.
• In the IO read cycle, all the operations are same as that
of memory read cycle.
• The difference is IO have eight bit port address ,
instead of 16-bit address.
• The 8-bit port address is carried by AD0-AD7.
• The higher order address A8-A15 is XXH.
 UNIT – 1 8085 PROCESSOR
Timing Diagram
• The = 1 in IO related operations.
 UNIT – 1 8085 PROCESSOR
Timing Diagram
IO Write Cycle:
• The microprocessor these cycles to write or send data to IO
device.
• The status of is high.
• The address of port is given by instruction.
• The time required to complete the IO write cycle is 3T states.
• In the IO Write cycle, all the operations are same as that of
memory read cycle.
• The difference is IO have eight bit port address , instead of
16-bit address.
• The 8-bit port address is carried by AD0-AD7.
• The higher order address A8-A15 is XXH.
 UNIT – 1 8085 PROCESSOR
Interrupts
Interrupts:
• Interrupt is signal send by an external device to the
processor, to request the processor to perform a
particular task or work.
• Mainly in the microprocessor based system the
interrupts are used for data transfer between the
peripheral and the microprocessor.
• The processor will check the interrupts always at
the 2nd T-state of last machine cycle.
•  If there is any interrupt it accept the interrupt and
send the INTA (active low) signal to the peripheral.
 UNIT – 1 8085 PROCESSOR
Interrupts
• The vectored address of particular interrupt is
stored in program counter.
• The processor executes an interrupt service routine
(ISR) addressed in program counter.
• The processor is returned to main program by RET
instruction.
Types of Interrupts:
It supports two types of interrupts.
Hardware
Software
 UNIT – 1 8085 PROCESSOR
Interrupts
Software interrupts:
• The software interrupts are program instructions. These instructions
are inserted at desired locations in a program. The 8085 has eight
software interrupts from RST 0 to RST 7.
 UNIT – 1 8085 PROCESSOR
Interrupts
Hardware interrupts:
• An external device initiates the hardware interrupts
and placing an appropriate signal at the interrupt
pin of the processor. If the interrupt is accepted then
the processor executes an interrupt service routine.
• The 8085 has five hardware interrupts
TRAP
RST 7.5
RST 6.5
RST 5.5
INTR
 UNIT – 1 8085 PROCESSOR
Interrupts
TRAP:
 This interrupt is a non-maskable interrupt.
 It is unaffected by any mask or interrupt enable.
 TRAP bas the highest priority and vectored interrupt.
 TRAP interrupt is edge and level triggered. This means that the TRAP must go high and
remain high until it is acknowledged.
  In sudden power failure, it executes a ISR and send the data from main memory to backup
memory.
 The signal, which overrides the TRAP, is HOLD signal. (i.e., If the processor receives HOLD
and TRAP at the same time then HOLD is recognized first and then TRAP is recognized).
 There are two ways to clear TRAP interrupt.

1. By resetting microprocessor (External signal)

2. By giving a high TRAP ACKNOWLEDGE (Internal signal)

 
 UNIT – 1 8085 PROCESSOR
Interrupts
RST 7.5:
•  The RST 7.5 interrupt is a maskable interrupt.
• It has the second highest priority.
• It is edge sensitive. ie. Input goes to high and no need to
maintain high state until it recognized.
• Maskable interrupt. It is disabled by,
1.DI instruction
 
2.System or processor reset. 3.After reorganization of
interrupt.

Enabled by EI instruction.
THANK YOU
20