Finite State Machines using D

Flip-Flops

Presented by
Deeksha Kumari MED2013
Sneha Kumari MED2306
 Contents
• Introduction
• Moore Machines
• Mealy Machines
• D Flip Flop
• Design Example
• Advantages of FSM using D Flip-Flops
• Applications
 Finite State Machine
A Finite State Machine (FSM) is a mathematical model used to design and describe the
behavior of systems that can exist in a finite number of states at any given time. It is
a computational abstraction that represents the dynamic behavior of a system
through a set of states, transitions between states, and an initial state.

• The basic components of an FSM are:

• States: The distinct conditions or situations that a system can be in. Each state
represents a specific mode or phase of the system.
• Transitions: The rules or conditions that determine when and how the system
moves from one state to another. Transitions are triggered by events or inputs.
• Initial State: The state in which the system starts when it is first activated or
initialized.
• Events/Inputs: External stimuli or occurrences that trigger state transitions. Events
can cause the system to change from one state to another.
• Actions/Outputs: Activities or changes associated with a state transition. These can
include performing specific tasks, generating outputs, or triggering further events.
Example: coin-operated turnstile
 There are two types of FSM

• Mealy Machine: In a Mealy machine, the outputs are

associated with transitions. The output depends on
both the current state and the input. The output is
produced at the time of the transition.
• Moore Machine: In a Moore machine, the outputs are
associated with states. The output depends only on
the current state. The output is produced after
entering the new state.
Moore Mealy type outputs
D Flip Flop
• A D flip-flop, also known as a Data or Delay flip-flop, is a type of
digital storage element in digital electronics. It is a fundamental
building block in sequential logic circuits and is widely used for
various applications, including memory storage, state machines, and
synchronization.
• A D flip-flop typically consists of a clock input (C or CLK), a data input (D), a Q
output, a complementary Q output (Q′), and sometimes a clear (CLR) or
preset (PR) input for additional control.

Symbol
Truth table

• When the clock signal is low, the flip flop holds its current state
and ignores the D input.
• When the clock signal is high, the flip flop samples and stores D
input.
• The value that was previously fed into the D input is reflected at
the flip flop’s Q output.
– If D = 0 then Q will be 0.
– If D = 1 then Q will be 1.
• The Q’ output of the flip flop is complemented by the Q output.
– If Q = 0 then Q’ will be 1.
– If Q = 1 then Q’ will be 0.
Characteristics table

Characteristics table
D is the input, and Q is current state, Qn
+ 1 is the next state outputs.
Qn+1 will always be zero when D is 0,
irrespective of current state of flip flop.
When the input of the flip flop is 1, next
state of flip flop will always be 1,
regardless of the current state of flip flop.
 Excitation Table

Here, Qn represents the current state of the flip

flop, and Dn represents the current input of the
flip flop. Where as Qn+1 represents the next
state of the flipflop.
•When the Qn is 0 and the Dn is also 0, then the
Qn+1 becomes 0. This situation explains the
condition of “hold” state.
•When the Qn is 0 but Dn is 1, then the Qn+1
becomes 1. This situation explains the condition
of “reset” state.
•When the Qn is 1 but Dn is 0, then the Qn+1
becomes 0. This situation explains the condition
of “hold” state.
•When the Qn is 1 and the Dn is also 1, then the
Qn+1 becomes 1. This situation explains the
condition of “reset” state.
 Characteristics Equation

• Qn+1 represents the output of flip flop at the

next clock cycle.
• Dn is the input to the flip flop at the current clock
cycle, and n represents the current clock cycle.
• This characteristic equation of D flip flop states
“that the output of the flip flop at the next clock
cycle will be equal to the input at the current
clock cycle“.
Example- Find the state diagram of the given
sequential circuit.
Example

A finite state machine (FSM) is implemented using the D flip-flops A and B, and
logic gates, as shown in the figure below. The four possible states of the FSM
are QAQB = 00, 01,10 and 11.
Assume that X1N is held at a constant logic level throughout the operation of
the FSM. When the FSM is initialized to the state QAQB = 00 and clocked, after
a few clock cycles, it starts cycling through a)all of the four possible states if
X1N = 1 b)three of the four possible states if X1N = 0 c)only two of the four
possible states if XIN = 1 d)only two of the four possible states if X1N = 0
Correct answer is option 'D'. Can you explain this answer?
 Advantages of FSM using D Flip-Flops

• Timing Control:
– D Flip-Flops help organize when state changes happen, making sure
everything stays in sync with the clock.
• Memory Function:
– D Flip-Flops act like memory, helping the FSM remember its current state
during transitions.
• Sequential Logic:
– They're great for building sequences of actions, which is what FSMs are all
about.
• Easy Design:
– Designing and understanding FSMs becomes simpler with D Flip-Flops, as
each flip-flop represents a state.
• Less Complexity:
– D Flip-Flops simplify FSMs by providing a modular design where each part
does a specific job.
 Application of FSM using D Flip-Flops
• Traffic Light Controllers
• Vending Machines
• Elevator Control Systems
• Sequence Detectors
• Digital Clocks
• Memory Systems
• Game Controllers
• Digital Security Systems
• Automated Systems
THANK YOU