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A7 24 vee
OUTPUT ENABLE
CHIP ENABLE AND
OUTPUT BUFFERS A6 23 AS
PROG LOGIC
A5 22 A9
V
V-GATING A4 21 All
DECODER
A3 20 OEivpp
AD-All
A2 Am9732/ 19 Al0
ADDRESS
INPUTS Am2732
X 32768-BIT Al 18 CE/PGM
DECODER CELL MATRIX
AO 17 07
00 16 06
01 10 15 05
MOS-490
02 11 14 04
GND 12 13 03
MODE SELECTION
~
MOS-491
CE/PGM OEivPp vee Outputs Top View
Mode (18) (20) (24) (9-11,13-17) Pin 1 is marked for orientation.
Read VIL VIL +5 DOUT
Standby VIH Don't Care +5 HighZ
Program VIL VPP +5 DIN
AO-A11: Addresses
Program Verify VIL VIL +5 DOUT 00-07: Outputs
CE/PGM: Chip Enable/Program
Program Inhibit VIH VPP +5 HighZ
OENPP: Output Enable
ORDERING INFORMATION
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Am97321Am2732
MAXIMUM RATINGS above which the useful life may be impaired
Storage Temperature -65 to +125°e
Ambient Temperature Under Bias
Voltage on All Inputs/Outputs (Except OENPP) with Respect to GND +6 to -O.3V
OENPP with Respect to GND +26.5 to -O.3V
READ OPERATION
DC CHARACTERISTICS
ooe ~ TA ~ +7o oe, vee = +5V ±5%
Parameters Description Test Conditions Min Max Units
III Input Load Current VIN = 5.25V 10 J.l.A
ILO Output Leakage Current VOUT = 5.25V 10 J.l.A
ICC1 VCC Current (Standby) CE = VIH, OE = VIL 30 mA
ICC2 VCC Current (Active) OE = CE = VIL 150 mA
AC CHARACTERISTICS
ooe ~ TA ~ + 7ooe, vee = +5V ±5%
Am2732 Am2732-6
Parameters Description Test Conditions Min Max Min Max Units
tACC Address to Output Delay CE = OE = VIL 450 550 ns
Output Load: 1 TTL gate and CL = 100pF
tCE CE to Output Delay OE = VIL 450 550 ns
Input Rise and Fall Times: ,.;;;20ns
tOE Output Enable to Output Delay Input Pulse Levels: 0.8 to 2.2V CE = VIL 120 120 ns
Timing Measurement Reference Level:
Output Enable High to
tDF Inputs: 1V and 2V CE = VIL 0 100 0 100 ns
Output Float
Outputs: 0.8V and 2V
tOH Address to Output Hold CE = OE = VIL 0 0 ns
CAPACITANCE (Note 1)
TA = +25e, f = 1MHz
Parameters Description Test Conditions Typ Max Units
CIN1 Input Capacitance (Except OEIVPP) VIN = OV 4 6 pF
CIN2 OENPP Input Capacitance VIN = OV 20 pF
COUT Output Capacitance VOUT = OV 12 pF
Note: 1. This parameter is only sampled and is not 100% tested.
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Am97321~732
AC WAVEFORMS (Note 1)
--------------------
ADDRESSES
ADDRESSES
VALID
'---------------------
'--------------
I------ICE-----i
1 ' - - - - - - + -- - - - - -
_7"""'l~-'7'-r-r- - - - - - ----~......"""\
HIGH Z HIGH Z
OUTPUT ----------------t-HH-t--+-<
-+-_______ ___
'-'a....J.........--a....... ~.4-L.J
MOS-492
Notes: 1. OE may be delayed up to 330ns after the falling edge of CE without impact on tACC.
2. tDF is specified from OE or CE, whichever occurs first.
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Am9732/Am2732
PROGRAM OPERATION
DC PROGRAMMING CHARACTERISTICS
TA = +25°e ±5°e, vee = 5V ±5%, VPP = 25V ±1V
PROGRAMMING WAVEFORMS
ADDRESSES ADDRESS N
tDV
OEivpp
tPRT tAH-t---l
CEjPGM
MOS-493
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Am9732/Am2732
ERASING THE Am2732 Enable (CE) is the power control and should be used for device
In order to clear all locations of their programmed contents, it is selection. Output Enable (OENPP) is the output control and
necessary to expose the Am2732 to an ultraviolet light source. A should be used to gate data to the output pins, independent of
dosage of 15 Wseconds/cm 2 is required to completely erase an device selection. Assuming that addresses are stable, address
Am2732. This dosage can be obtained by eXRosure to an ul- access time (tACC) is equal to the delay from CE to output (tCE).
traviolet lamp [(wavelength of 2537 Angstroms (A)] with intensity Data is available at the outputs 120ns (tOE) after the falling edge
of 12000l1W/cm2 for 15 to 20 minutes. The Am2732 should be of OE, assuming that CE has been low and addresses have been
about one inch from the source and all filters should be removed stable for at least tACC - tOE.
from the UV light source prior to erasure. STANDBY MODE
It is important to note that the Am2732, and similar devices, will The Am2732 has a standby mode which reduces the active
erase with light sources having wavelengths shorter than 4000 power dissipation by 80%, from 787mWto 157mW. The Am2732
Angstroms. Although erasure times will be much longer than with is placed in the standby mode by applying a TTL high signal to the
UV sources at 2537'&', nevertheless the exposure to fluorescent CE input. When in standby mode, the outputs are in a high
light and sunlight will eventually erase the Am2732, and exposure impedance state, independent of the OE input.
to them should be prevented to realize maximum system relia-
bility. If used in such an environment, the package windows OUTPUT OR-TIEING
should be covered by an opaque label or substance. To accommodate multiple memory connections, a 2 line control
PROGRAMMING THE Am2732 function is provided to allow for:
1. Low memory power dissipation
Upon delivery, or after each erasure the Am2732 has all 32768 2. Assurance that output bus contention will not occur.
bits in the "1", or high state. "O"s are loaded into the Am2732
through the procedure of programming. It is recommended that CE be decoded and used as the primary
device selecting function, while OE be made a common connec-
The programming mode is entered when +25V is applied to the
tion to all devices in the array and connected to the READ line
OENPP pin. A 0.1p.F capaCitor must be placed across OENPP from the system control bus. This assures that all deselected
and ground to suppress spurious voltage transients which may
memory devices are in their low-power standby mode and that
damage the device. The address to be programmed is applied to the output pins are only active when data is desired from a
the proper address pins. 8-bit patterns are placed on the respec-
particular memory device.
tive data output pins. The voltage levels should be standard TTL .
levels. When both the address and data are stable, a 50msec, PROGRAM INHIBIT
TTL low level pulse is applied to the CE/PGM input to accomplish Programming of multiple Am2732s in parallel with different data is
the programming. also easily accomplished. Except for CE/PGM, all like inputs
The procedure can be done manually, address by address, ran- (including OE) of the parallel Am2732s may be common. A TTL
domly, or automatically via the proper circuitry. All that is required level program pulse applied to an Am2732's CE/PGM input with
is that one 50msec program pulse be applied at each address to VPP at 25V will program that Am2732. A high level CE/PGM input
be programmed. It is necessary that this program pulse width not inhibits the other Am2732 from being programmed.
exceed 55msec. Therefore, applying a DC low level to the CEI
PROGRAM VERIFY
PGM input is prohibited when programming.
A verify should be performed on the programmed bits to deter-
READ MODE mine that they were correctly programmed. The verify must be
The Am2732 has two control functions, both of which must be performed with OENPP and CE at VIL. Data should be verified
logically satisfied in order to obtain data at the outputs. Chip tDV after the falling edge of CEo
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