Fig 1.

Resource centers and participating institutes

2.2.2 ACHIEVEMENTS IN THE MAJOR ELEMENTS OF THE PROGRAMME

Establishing State–of-the art VLSI Design Laboratory where VLSI Design Laboratories
were established at 32 institutions equipped with State-of-the-art Hardware platforms and
Electronic Design Automation (EDA) Tools

Generation of manpower in VLSI Design area at various levels under the program. The
students of RCs and PIs at various levels such as B.Tech, M.Tech and Ph.D were introduced
to specialized topics in VLSI Design. A model curriculum was also developed and adopted by
the Institutions. The primary target of the Programme was to generate substantial number of
manpower at M.Tech level having VLSI design as their primary specialization.

Instruction Enhancement Program (IEP) for faculties of PIs were organised. 23

Instruction Enhancement Programmes (IEPs) on different topics/areas were conducted at
various RC/PI locations by Resource Centres for training faculty of Participating Institutions.
A total of 654 faculties/Lab Engineers of PIs were trained through this programme

Initiation of India Chip Program was carried out. Fabrication of fourteen chips, 5 in
single mode and 9 in “Multi Project Wafer (MPW)” mode was undertaken for Siliconization of
Analog and Digital designs done by students of various

RCs and PIs. In the five single mode design - IIT D prototyped 2 individuals designs
whereas each of IIT M, IIT G and IIT Kharagpur prototyped single designs. For the design
undertaken by IIT Kharagpur sub blocks were designed by NIT Durgapur, Jadavpur University
and IIT Kharagpur itself.

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Industry ready Specialised Manpower has been generated in VLSI/ System Design Area at
B.Tech, M.Tech and PhD level.

State-of-the-Art VLSI Design Laboratories were established at 60 Institutions equipped

with Hardware platforms and Electronic Design Automation (EDA) Tools from Cadence/
Synopsys/ Mentor/ Xilinx. These labs are not only used by students involved under
SMDPC2SD project to undertake design of VLSI circuits but also by students from other
Departments & nearby institutes

Under the programme, in order to inculcate the culture of Chip to System development
activity at Institutions, 15 Systems/SoCs were undertaken by 10 RCs for development of
Working Prototype. For each system project, End users were identified and specifications
were finalized in consultation with them. The End users were also involved in the Project
Review Committee for continuous monitoring of the Project.

To provide the exposure of complete design cycle of Chip development, ASICs designs
were also undertaken by Participating Institutions who were part of previous SMDP
programmes. Some of the ASICs designed by the PIs were also used in the 15 Working
Prototype SoCs/ Systems, being developed for Strategic & Societal sectors. Under the
Programme, total 150 ASIC fabricated and being fabricated at SCL and outside foundry as
depicted in Fig 2. below.

Fig 2. Total ASIC fabricated at SCL and outside foundry

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 Under the programme, SMDP-C2SD website was developed by CDAC Delhi & being
used to disseminate information including educational materials generated through IEP, Short-
term courses, training programme on EDA tools, Review meeting, Information about Patent
registered, Interactive forums to discuss design issues among researchers from 60 PIs. The
SMDP model of MeitY has been a successful model for targeted manpower development in a
niche area. The program has successfully inculcated the culture of System-on-Chip/ System
Development using mostly in-house designed ASICs / ICs at Academic institutions along with
generation of expertise.

Fig 3. Website of C2SD

2.4 CHIP 2 STARTUP

Ministry of Electronics and Information Technology has come out with National Policy
on Electronics 2019 (NPE-2019) with a vision to position India as a global hub for Electronics
System Design and Manufacturing (ESDM) by encouraging and driving capabilities in the
country for developing core components, including chipsets, and creating an enabling
environment for the Industry to compete globally. One of the objectives of National Policy of
Electronics is to promote domestic manufacturing including core components and materials
and to reduce dependence on import of electronic goods by focusing on skill, technology,
scale and the global market with a target to achieve the turnover of USD 400 billion
(approximately INR 26,00,000 crore) by 2025.To achieve this target, some of the strategies
identified in NPE 2019 are to (i) encourage participation of academic institutes in smaller cities
in addition to premier institutes, (ii) bring collaborative R&D between academia and industry
iii) Provide support to start-ups in emerging areas/ technologies from supporting the concept
to development/ prototyping of products, including the complete value chain (iv) Set up a
framework for creation of an ecosystem for promoting design of IPs in the country.

In line with the objective and vision of NPE-2019, an umbrella programme “Chips to
Startup (C2S)” Programme has been proposed which not only aims at developing Specialized
Manpower in VLSI/Embedded System Design domain but also addresses each entity of the
Electronics value chain via Specialized Manpower training, Creation of reusable IPs

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repository, Design of application-oriented Systems/ASICs/FPGAs and deployment by
academia/ R&D organization by way of leveraging the expertise available at Startups/MSMEs.

The main objectives of the Chips to Startup Programme (C2S) are: i. Generating
Industry-ready manpower in System/ SoC Design area for creating vibrant fabless chip design
ecosystem in the country. ii. Promoting industry-led R&D, translational research and
strengthening Industry Academia collaboration. iii. Leapfrogging in ESDM space by way of
inculcating the culture of developing reusable IP Cores & developing ASIC/ SoC/ Systems for
societal/ strategic sectors. 33 iv. Broaden the base of ASIC / IC design in the Country by
accommodating more academic institutions, start-ups for design of IPs / ASICs / Systems/
SoCs. v. Protection of Intellectual Property generated etc. vi. To inculcate the culture of
entrepreneurship among students & researchers by way of incubating startups.

Fig 4. Chip to Startup scheme

2.4.1 PARTICIPATING INSTITUTIONS

The programme would be implemented at about 100 academic institutions/R&D
organizations across the Country. Besides them, Start-ups and MSMEs can also participate
in the programme if they had submitted their proposals under Academia- Industry
Collaborative Project, Grand Challenge/ /Hackathons/RFP for development of System/SoC/IP
Core(s).

Under the Programme, based on the Institutions expertise, Technology Readiness Level
(TRL) and design experience acquired during earlier SMDP Programmes, invited calls for
proposal in three different categories from the Institutions, Start-ups and MSMEs for
development of frugal solutions in areas like Healthcare/ Agriculture/ Energy Environment/
Intelligent Transport /Emerging Technology/Safety & Security etc. The purpose of this