Professional Documents
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Applications
• DC motor driving in full or half bridge
configuration
• All types of resistive, inductive and capacitive
62GRXEOHLVODQG loads
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Description
Features The VN5770AKP-E is a device formed by three
monolithic chips housed in a standard SO-28
Type RDS(on) IOUT (typ) VCC package: a double high-side and two low-side
switches. The double high-side is made using
VN5770AKP-E 280 mΩ(1) 8.5 A 36 V STMicroelectronics® VIPower® M0-5 technology,
1. Total resistance of one side in bridge configuration while the low-side switches are fully protected
VIPower M0-3 OMNIFET II. This device is
suitable to drive a DC motor in a bridge
• ECOPACK®: lead free and RoHS compliant configuration as well as to be used as a quad
• Automotive Grade: compliance with AEC switch for any low voltage application.
guidelines
The dual high-side switches integrate built in non
• General features latching thermal shutdown with thermal
– Inrush current management by active hysteresis. An output current limiter protects the
power limitation on the high-side switches device in overload condition. In case of long
– Very low standby current overload duration, the device limits the dissipated
– Very low electromagnetic susceptibility power to a safe level up to thermal shutdown
intervention. An analog current sense pin delivers
– Compliance with European directive
a current proportional to the load current
2002/95/EC
(according to a known ratio) and indicates
• Protection overtemperature shutdown of the relevant
– High-side drivers undervoltage shutdown high-side switch through a voltage flag.
– Overvoltage clamp The low-side switches have built in non latching
– Output current limitation thermal shutdown with thermal hysteresis, linear
– High and low-side overtemperature current limitation and overvoltage clamping.
shutdown
Fault feedback for overtemperature shutdown of
– Short circuit protection the low-side switch is indicated by the relevant
– ESD protection input pin current consumption going up to the fault
• Diagnostic functions sink current flag.
– Proportional load current sense
Contents
3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 Electrical characteristics for dual high-side switch . . . . . . . . . . . . . . . . . . 10
5 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1 Maximum demagnetization energy (VCC = 13.5 V) . . . . . . . . . . . . . . . . . 24
7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.1 SO-28 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.2 SO-28 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
List of tables
List of figures
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Stressing the device above the rating listed in Table 3 and Table 4 may cause permanent
damage to the device. These are stress ratings only and operation of the device at these or
any other conditions above those indicated in the Operating sections of this specification is
not implied. Exposure to the conditions in Section 2.1: Absolute maximum ratings for
extended periods may affect device reliability.
3 Electrical characteristics
Operating supply
VCC 4.5 13 36 V
voltage
VUSD Undervoltage shutdown 3.5 4.5 V
Undervoltage shutdown
VUSDhyst 0.5 V
hysteresis
IOUT = 3 A; Tj = 25 °C 160 mΩ
RON On-state resistance IOUT = 3 A; Tj = 150 °C 320 mΩ
IOUT = 3 A; VCC = 5 V; Tj = 25 °C 210 mΩ
Vclamp Clamp Voltage IS = 20 mA 41 46 52 V
Off-state; VCC = 13 V; Tj = 25 °C;
2(1) 5(1) µA
VIN = VOUT = VSENSE = 0 V
IS Supply current
On-state; VCC = 13 V; VIN = 5 V;
3 6 mA
IOUT = 0 A
VIN = VOUT = 0 V; VCC = 13 V;
0 3 µA
Off-state output Tj = 25 °C
IL(off)
current(2) VIN = VOUT = 0 V; VCC = 13 V;
0 5 µA
Tj = 125 °C
Output - VCC diode
VF -IOUT = 3 A; Tj = 150 °C 0.7 V
voltage(2)
1. PowerMOS leakage included
2. For each channel
VCC = 13 V 6 8.5 12 A
IlimH DC Short circuit current
5 V < VCC < 36 V 12 A
Short circuit current
IlimL VCC = 13 V; TR < Tj < TTSD 3.5 A
during thermal cycling
TTSD Shutdown temperature 150 175 200 °C
TR Reset temperature TRS + 1 TRS + 5 °C
Thermal reset of
TRS 135 °C
STATUS
Thermal hysteresis
THYST 7 °C
(TTSD-TR)
Turn-off output voltage IOUT = 1 A; VIN = 0;
VDEMAG VCC-41 VCC-46 VCC-52 V
clamp L = 20 mH
IOUT = 0.03 A;
Output voltage drop
VON Tj = -40 °C to 150 °C 25 mV
limitation
(see Figure 4)
1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related
diagnostic signals must be used together with a proper software strategy. If the device is subjected to
abnormal conditions, this software must limit the duration and number of activation cycles
IOUT = 0.08 A;
K0 IOUT/ISENSE VSENSE = 0.5 V; 850 1450 2120
Tj = -40°C to 50°C
IOUT = 0.35 A; VSENSE = 0.5V;
K1 IOUT/ISENSE Tj = -40°C to 150°C 840 1360 2000
Tj = 25°C to 150°C 980 1360 1740
IOUT = 3A; VSENSE = 4V;
K2 IOUT/ISENSE 1200 1270 1350
Tj = -40°C to 150°C
IOUT = 4A; VSENSE = 4V;
K3 IOUT/ISENSE 1200 1270 1350
Tj = -40°C to 150°C
IOUT = 0A; VSENSE = 0V;
0 1 µA
VIN = 0V; Tj = -40°C to 150°C
ISENSE0 Analog sense current
IOUT = 0A; VSENSE = 0V;
0 2 µA
VIN = 5V; Tj = -40°C to 150°C
Max analog sense output
VSENSE IOUT = 5A; RSENSE = 3.9 KΩ 5 V
voltage
Analog sense output voltage
VSENSEH V = 13V; RSENSE = 3.9 KΩ 9 V
in overtemperature condition CC
Analog sense output current
ISENSEH V = 13V 8 mA
in overtemperature condition CC
VSENSE<4 V; 0.35 A<Iout<5 A;
Delay response time from
tDSENSE2H ISENSE = 90% of ISENSE max 70 300 µs
rising edge of INPUT pin
(see Figure 5)
VSENSE<4 V; 0.35 A<Iout<5 A;
Delay response time from ISENSE = 10% of ISENSE max
tDSENSE2L 100 250 µs
falling edge of INPUT pin
(see Figure 5)
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H L 0
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H L 0
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H H < Nominal
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Figure 10. Input high level Figure 11. Input hysteresis voltage
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Figure 12. On-state resistance vs Tcase Figure 13. On-state resistance vs VCC
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Drain-source clamp
VCLAMP VIN = 0 V; ID = 1.5 A 40 45 55 V
voltage
Drain-source clamp
VCLTH VIN = 0 V; ID = 2 mA 36 V
threshold voltage
VINTH Input threshold voltage VDS = VIN; ID = 1 mA 0.5 2.5 V
Supply current from
IISS VDS = 0 V; VIN = 5 V 100 150 µA
input pin
Table 12. On
Symbol Parameter Test conditions Min Typ Max Unit
Forward
gfs VDD = 13 V; ID = 1.5 A — 2.5 — S
transconductance
COSS Output capacitance VDS = 13 V; f = 1 MHz; VIN = 0 V — 150 — pF
VDD = 15 V; ID = 3 A; Vgen = 5 V;
(dI/dt)on Turn-on current slope — 3.0 A/µs
Rgen = RIN MINn = 220 Ω
VDD = 12 V; ID = 3 A; VIN = 5 V;
Qi Total input charge — 9.0 nC
Igen = 2.13 mA
Table 16. Protection and diagnostics (-40 °C < Tj < 150 °C, unless otherwise specified)
Symbol Parameter Test conditions Min Typ Max Unit
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input voltage (part 1) input voltage (part 2)
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Note: Mostly motor bridge drivers use a reverse battery protection diode (D) inside supply rail.
This diode prevents a reverse current flow back to Vbatt in case the bridge gets disabled via
the logic inputs while motor inductance still carries energy. In order to prevent a hazardous
overvoltage at circuit supply terminal (Vcc), a blocking capacitor (C) is needed to limit the
voltage overshoot. As basic orientation, 50 µF per 1 A load current in recommended. In
alternative, also a Zener protection (Z) is suitable. Even if a reverse polarity diode is not
present, it is recommended to use a capacitor or zener at Vcc because a similar problem
appears in case supply terminal of the module has intermittent electrical contact to the
battery or gets disconnected while motor is operating.
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Note: Layout condition of Rth and Zth measurements (PCB FR4 area= 58 mm x 58 mm, PCB
thickness = 2 mm, Cu thickness = 35 mm, Copper areas: from minimum pad layout to
16 cm2).
Figure 39. Auto and mutual Rthj-amb vs PCB copper area in open box free air
condition
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Note: See Figure 38. For more detailed information see Table 17 and Table 18.
Note: Calculation is valid in any dynamic operating condition. Pd values set by user.
Figure 40. SO-28 HSD thermal impedance junction ambient single pulse
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Z THδ = R TH ⋅ δ + Z THtp ( 1 – δ )
where δ = tp ⁄ T
R1 = R7 (°C/W) 1
R2 = R8 (°C/W) 1.8
R3 = R11 = R17 (°C/W) 3.5
R4 (°C/W) 13.5
R5 = R13 = R19 (°C/W) 10.5
R6 = R14 = R20 (°C/W) 62.28 52.28 44.28 32.28
R9 = R15 (°C/W) 0.24
R10 = R16 (°C/W) 1.2
R12 (°C/W) 15.2
R18 (°C/W) 15.5
R21 = R22 = R23 (°C/W) 150
R24 (°C/W) 150 52.28 44.28 32.28
C1 = C7 (W·s/°C) 0.0008
C2 = C8 (W·s/°C) 0.001
C3 = C11 = C17 (W·s/°C) 0.008
C5 = C13 = C19 (W·s/°C) 0.2
C6 = C14 = C20 (W·s/°C) 1.6 1.61 1.7 3.25
C9 = C15 (W·s/°C) 0.00015
C10 = C16 (W·s/°C) 0.0005
Note: A blank space means that the value is the same as the previous one.
7 Package information
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Ref. Millimeters
A 2.35 2.65
A1 0.10 0.30
B 0.33 0.51
C 0.23 0.32
D(1) 17.70 18.10
Ref. Millimeters
E 7.40 7.60
e 1.27
H 10.0 10.65
h 0.25 0.75
L 0.40 1.27
k 0° 8°
ddd 0.10
1. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side.
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8 Order codes
9 Revision history
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