Unit-1

1.1 Computer Organization and Architecture

Computer Architecture is a functional description of requirements and design

implementation for the various parts of a computer. It deals with the functional
behavior of computer systems. It comes before the computer organization while
designing a computer.
Architecture describes what the computer does.
Computer Organization comes after the decision of Computer Architecture first.
Computer Organization is how operational attributes are linked together and
contribute to realizing the architectural specification. Computer Organization deals
with a structural relationship.

The organization describes how it does it.

Computer Architecture refers to those attributes of a system that have a direct impact on the logical
execution of a program. Examples:

 the instruction set

 the number of bits used to represent various data types
 I/O mechanisms
 memory addressing techniques

Computer Organization refers to the operational units and their interconnections that realize the
architectural specifications. Examples are things that are transparent to the programmer:

 control signals
 interfaces between computer and peripherals
 the memory technology being used

So, for example, the fact that a multiply instruction is available is a computer architecture issue. How
that multiply is implemented is a computer organization issue.

Architecture is those attributes visible to the programmer

 Instruction set, number of bits used for data representation, I/O mechanisms, addressing
techniques.
 e.g. Is there a multiply instruction?

Organization is how features are implemented

 Control signals, interfaces, memory technology.

 e.g. Is there a hardware multiply unit or is it done by repeated addition?
 1.2 Computer Architecture VS Computer Organization

Computer Architecture Computer Organization

Computer Architecture is concerned with the way Computer Organization is concerned with the
hardware components are connected together to form a structure and behavior of a computer system as
computer system. seen by the user.

It acts as the interface between hardware and software. It deals with the components of a connection in a
system.

Computer Architecture helps us to understand the Computer Organization tells us how exactly all the
functionalities of a system. units in the system are arranged and
interconnected.

A programmer can view architecture in terms of Whereas Organization expresses the realization of
instructions, addressing modes and registers. architecture.

While designing a computer system architecture is An organization is done on the basis of

considered first. architecture.

Computer Architecture deals with high-level design Computer Organization deals with low-level
issues. design issues.

Architecture involves Logic (Instruction sets, Organization involves Physical Components

Addressing modes, Data types, Cache optimization) (Circuit design, Adders, Signals, Peripherals)

1. 3 Functional unit of digital system and their interconnections

A typical digital computer system has five basic functional elements:

1. Input unit
2. Central Processing Unit
3. Memory unit, Arithmetic & logical unit
4. Control unit
5. Output unit
Input unit
o Input units are used by the computer to read the data. The most commonly used input
devices are keyboards, mouse, joysticks, trackballs, microphones, etc.
o However, the most well-known input device is a keyboard. Whenever a key is
pressed, the corresponding letter or digit is automatically translated into its
corresponding binary code and transmitted over a cable to either the memory or the
processor.

Central processing unit

o Central processing unit commonly known as CPU can be referred as an electronic
circuitry within a computer that carries out the instructions given by a computer
program by performing the basic arithmetic, logical, control and input/output (I/O)
operations specified by the instructions.

Memory unit
o The Memory unit can be referred to as the storage area in which programs are kept
which are running, and that contains data needed by the running programs.
o The Memory unit can be categorized in two ways namely, primary memory and
secondary memory.
 o It enables a processor to access running execution applications and services that are
temporarily stored in a specific memory location.
o Primary storage is the fastest memory that operates at electronic speeds. Primary
memory contains a large number of semiconductor storage cells, capable of storing a
bit of information. The word length of a computer is between 16-64 bits.
o It is also known as the volatile form of memory, means when the computer is shut
down, anything contained in RAM is lost.
o Cache memory is also a kind of memory which is used to fetch the data very soon.
They are highly coupled with the processor.
o The most common examples of primary memory are RAM and ROM.
o Secondary memory is used when a large amount of data and programs have to be
stored for a long-term basis.
o It is also known as the Non-volatile memory form of memory, means the data is
stored permanently irrespective of shut down.
o The most common examples of secondary memory are magnetic disks, magnetic
tapes, and optical disks.

Arithmetic & logical unit

o Most of all the arithmetic and logical operations of a computer are executed in the
ALU (Arithmetic and Logical Unit) of the processor. It performs arithmetic
operations like addition, subtraction, multiplication, division and also the logical
operations like AND, OR, NOT operations.

Control unit
o The control unit is a component of a computer's central processing unit that
coordinates the operation of the processor. It tells the computer's memory,
arithmetic/logic unit and input and output devices how to respond to a program's
instructions.
o The control unit is also known as the nerve center of a computer system.
o Let's us consider an example of addition of two operands by the instruction given as
Add LOCA, RO. This instruction adds the memory location LOCA to the operand in
 the register RO and places the sum in the register RO. This instruction internally
performs several steps.

Output Unit
o The primary function of the output unit is to send the processed results to the user.
Output devices display information in a way that the user can understand.
o Output devices are pieces of equipment that are used to generate information or any
other response processed by the computer. These devices display information that has
been held or generated within a computer.
o The most common example of an output device is a monitor.

1.4 BUSES
A bus is a high-speed internal connection. Buses are used to send control signals and
data between the processor and other components. Bus is a group of conducting
wires which carries information; all the peripherals are connected to microprocessor
through Bus.

The following are a few points to describe a computer bus:-

 A bus is a group of lines/wires which carry computer signals.

 A bus is the means of shared transmission.
 Lines are assigned to providing descriptive names. — carries a single electrical
signal, e.g. 1-bit memory address, data bits series, or timing control that turns
the device on or off.
 Data can be transferred from one computer system location to another (between
different I / O modules, memory, and CPU).
 The bus is not only cable but also hardware (bus architecture), protocol,
program, and bus controller.
Three types of bus are used.

Address bus - carries memory addresses from the processor to other components such as
primary storage and input/output devices. The address bus is unidirectional.

 It is a group of conducting wires which carries address only.Address bus is

unidirectional because data flow in one direction, from microprocessor to
memory or from microprocessor to Input/output devices
 Length of Address Bus is 16 Bit.
 It can transfer maximum 16 bit address which means it can address 65, 536
different memory location.
 The Length of the address bus determines the amount of memory a system
can address.Such as a system with a 32-bit address bus can address 2^32
memory locations.If each memory location holds one byte, the addressable
memory space is 4 GB.

Data bus - carries the data between the processor and other components. The data
bus is bidirectional.

It is a group of conducting wires which carries Data only.Data bus is

bidirectional because data flow in both directions, from microprocessor to
memory or Input/Output devices and from memory or Input/Output devices
to microprocessor.

Length of Data Bus is 8 Bit.

When it is write operation, the processor will put the data (to be written) on the data
bus, when it is read operation, the memory controller will get the data from specific
memory block and put it into the data bus.
The width of the data bus is directly related to the largest number that the bus can
carry, such as an 8 bit bus can represent 2 to the power of 8 unique values, this
equates to the number 0 to 255.A 16 bit bus can carry 0 to 65535.

Control bus - carries control signals from the processor to other components. The control
bus also carries the clock's pulses. The control bus is unidirectional.

It is a group of conducting wires, which is used to generate timing and control

signals to control all the associated peripherals, microprocessor uses control bus to
process data, that is what to do with selected memory location. Some control
signals are:

 Memory read
 Memory write
 I/O read
 I/O Write
 Opcode fetch
If one line of control bus may be the read/write line.If the wire is low (no electricity
flowing) then the memory is read, if the wire is high (electricity is flowing) then the
memory is written.

1.5 BUS Arbitration

Bus Arbitration refers to the process by which the current bus master accesses and
then leaves the control of the bus and passes it to another bus requesting processor
unit. The controller that has access to a bus at an instance is known as a Bus
master.
A conflict may arise if the number of processors try to access the common bus at
the same time, but access can be given to only one of those. Only one processor or
controller can be Bus master at the same point in time. To resolve these conflicts,
the Bus Arbitration procedure is implemented to coordinate the activities of all
devices requesting memory transfers. The selection of the bus master must take into
account the needs of various devices by establishing a priority system for gaining
access to the bus. The Bus Arbiter decides who would become the current bus
master.
 There are three bus arbitration methods:

(i) Daisy Chaining method: It is a simple and cheaper method where all the bus
masters use the same line for making bus requests. The bus grant signal serially
propagates through each master until it encounters the first one that is requesting
access to the bus. This master blocks the propagation of the bus grant signal,
therefore any other requesting module will not receive the grant signal and hence
cannot access the bus.
During any bus cycle, the bus master may be any device – the processor or any
DMA controller unit, connected to the bus.

Advantages:
 Simplicity and Scalability.
 The user can add more devices anywhere along the chain, up to a certain
maximum value.
Disadvantages:
 The value of priority assigned to a device depends on the position of the master
bus.
 Propagation delay arises in this method.
 If one device fails then the entire system will stop working.

(ii) Polling or Rotating Priority method: In this, the controller is used to generate
the address for the master(unique priority), the number of address lines required
depends on the number of masters connected in the system. The controller generates
a sequence of master addresses. When the requesting master recognizes its address,
it activates the busy line and begins to use the bus.

 Here all bus masters use the same line for bus request.
 Here controller generates binary address for the master. (To connect 8 bus masters we
need 3 address lines.
  In response to a bus request, the controller “polls” the bus masters by sending a
sequence of bus master address on address lines.
 When requesting master recognizes its address, it activates the bus busy lines and
takes control of the bus.

Advantages –
 This method does not favor any particular device and processor.
 The method is also quite simple.
 Priority flexible.
 One module fails, entire system does not fail.

Disadvantages –
 Adding bus masters is difficult as increases the number of address lines of the
circuit.
 If one device fails then the entire system will not stop working.
(iii) Fixed priority or Independent Request method –
In this, each master has a separate pair of bus request and bus grant lines and each
pair has a priority assigned to it.
The built-in priority decoder within the controller selects the highest priority
request and asserts the corresponding bus grant signal.

 All bus masters have their individual bus request and bus grant lines.
 The controller thus knows which master has requested, so bus is granted t that master.
 Priorities of the masters are predefined so on simultaneous bus requests, the bus is
granted based on the priority, provided the bus busy line is not active.
 The controller consists of encoder and decoder logic for priorities.
Advantages –
 This method generates a fast response.
 Speed independent of no. of devices connected.
Disadvantages –
 Hardware cost is high as a large no. of control lines is required.

1.6 Computer Registers

Registers are a type of computer memory used to quickly accept, store, and transfer data and
instructions that are being used immediately by the CPU. The registers used by the CPU are
often termed as Processor registers.

A processor register may hold an instruction, a storage address, or any data (such as bit
sequence or individual characters).

The computer needs processor registers for manipulating data and a register for holding a
memory address. The register holding the memory location is used to calculate the address of
the next instruction after the execution of the current instruction is completed.

Register Symbol Number of bits Function

Data register DR 16 Holds memory operand

Address register AR 12 Holds address for the memory

Accumulator AC 16 Processor register

Instruction register IR 16 Holds instruction code

Program counter PC 12 Holds address of the instruction

Temporary register TR 16 Holds temporary data

Input register INPR 8 Carries input character

Output register OUTR 8 Carries output character

o The Memory unit has a capacity of 4096 words, and each word contains 16 bits.
o The Data Register (DR) contains 16 bits which hold the operand read from the
memory location.
o The Memory Address Register (MAR) contains 12 bits which hold the address for the
memory location.
 o The Program Counter (PC) also contains 12 bits which hold the address of the next
instruction to be read from memory after the current instruction is executed.
o The Accumulator (AC) register is a general purpose processing register.
o The instruction read from memory is placed in the Instruction register (IR).
o The Temporary Register (TR) is used for holding the temporary data during the
processing.
o The Input Registers (IR) holds the input characters given by the user.
o The Output Registers (OR) holds the output after processing the input data.

1.7 Bus and Memory Transfers

A digital system composed of many registers, and paths must be provided to transfer
information from one register to another. The number of wires connecting all of the registers
will be excessive if separate lines are used between each register and all other registers in the
system.

A bus structure, on the other hand, is more efficient for transferring information between
registers in a multi-register configuration system.

A bus consists of a set of common lines, one for each bit of register, through which binary
information is transferred one at a time. Control signals determine which register is selected
by the bus during a particular register transfer.

Note: The number of multiplexers needed to construct the bus is equal to the number of bits in each
register. The size of each multiplexer must be 'k * 1' since it multiplexes 'k' data lines. For instance, a
common bus for eight registers of 16 bits each requires 16 multiplexers, one for each line in the bus. Each
multiplexer must have eight data input lines and three selection lines to multiplex one significant bit in the
eight registers.
The two selection lines S1 and S2 are connected to the selection inputs of all four
multiplexers. The selection lines choose the four bits of one register and transfer them into
the four-line common bus.

When both of the select lines are at low logic, i.e. S1S0 = 00, the 0 data inputs of all four
multiplexers are selected and applied to the outputs that forms the bus. This, in turn, causes
the bus lines to receive the content of register A since the outputs of this register are
connected to the 0 data inputs of the multiplexers.

Similarly, when S1S0 = 01, register B is selected, and the bus lines will receive the content
provided by register B.
 Memory Transfer
Most of the standard notations used for specifying operations on memory transfer are stated
below.

o The transfer of information from a memory unit to the user end is called
a Read operation.
o The transfer of new information to be stored in the memory is called
a Write operation.
o A memory word is designated by the letter M.
o We must specify the address of memory word while writing the memory transfer
operations.
o The address register is designated by AR and the data register by DR.
o Thus, a read operation can be stated as:

1. Read: DR ← M [AR]
o The Read statement causes a transfer of information into the data register (DR) from
the memory word (M) selected by the address register (AR).
o And the corresponding write operation can be stated as:

1. Write: M [AR] ← R1
o The Write statement causes a transfer of information from register R1 into the
memory word (M) selected by address register (AR).
1.8 Processor organization
A instruction is of various length depending upon the number of addresses it
contain. Generally CPU organization are of three types on the basis of number of
address fields:
1. Single Accumulator organization
2. General register organization
3. Stack organization

i) Single Accumulator based CPU organization

In this type of CPU organization, the accumulator register is used implicitly for
processing all instructions of a program and storing the results into the accumulator.
The instruction format that is used by this CPU Organisation is the One address
field. Due to this, the CPU is known as One Address Machine.
The main points about Single Accumulator based CPU Organisation are:
1. In this CPU Organization, the first ALU operand is always stored into the
Accumulator and the second operand is present either in Registers or in the
Memory.
2. Accumulator is the default address thus after data manipulation the results are
stored into the accumulator.
3. One address instruction is used in this type of organization.
The format of instruction is: Opcode + Address
Opcode indicates the type of operation to be performed.
Mainly two types of operation are performed in a single accumulator based CPU
organization:
1. Data transfer operation –
In this type of operation, the data is transferred from a source to a destination.
For ex: LOAD X, STORE Y
Here LOAD is a memory read operation that is data is transferred from memory to
accumulator and STORE is a memory write operation that is data is transferred
from the accumulator to memory.
2. ALU operation –
In this type of operation, arithmetic operations are performed on the data.
For ex: MULT X
where X is the address of the operand. The MULT instruction in this example
performs the operation,
AC <-- AC * M[X]
AC is the Accumulator and M[X] is the memory word located at location X.
This type of CPU organization is first used in PDP-8 processors and is used for
process control and laboratory applications. It has been totally replaced by the
introduction of the new general register-based CPU.
Advantages –
 One of the operands is always held by the accumulator register. This results in
short instructions and less memory space.
 The instruction cycle takes less time because it saves time in instruction fetching
from memory.
Disadvantages –
 When complex expressions are computed, program size increases due to the
usage of many short instructions to execute it. Thus memory size increases.
 As the number of instructions increases for a program, the execution time
increases.

ii) General Register based CPU Organization

When we are using multiple general-purpose registers, instead of a single

accumulator register, in the CPU Organization then this type of organization is
known as General register-based CPU Organization. In this type of organization,
the computer uses two or three address fields in their instruction format. Each
address field may specify a general register or a memory word. If many CPU
registers are available for heavily used variables and intermediate results, we can
avoid memory references much of the time, thus vastly increasing program
execution speed, and reducing program size.
For example:
MULT R1, R2, R3
This is an instruction of an arithmetic multiplication written in assembly language.
It uses three address fields R1, R2, and R3. The meaning of this instruction is:
R1 <-- R2 * R3
This instruction also can be written using only two address fields as:
MULT R1, R2
In this instruction, the destination register is the same as one of the source registers.
This means the operation
R1 <-- R1 * R2
The advantages of General register-based CPU organization –
 The efficiency of the CPU increases as large number of registers are used in this
organization.
 Less memory space is used to store the program since the instructions are
written in a compact way.
The disadvantages of General register based CPU organization –
 Care should be taken to avoid unnecessary usage of registers. Thus, compilers
need to be more intelligent in this aspect.
 Since a large number of registers are used, thus extra cost is required in this
organization.
General register CPU organization of two types:
1. Register-memory reference architecture (CPU with less register) –
In this organization Source 1 is always required in the register, source 2 can be
present either in the register or in memory. Here two address instruction formats
are compatible instruction formats.
2. Register-register reference architecture (CPU with more register) –
In this organization, ALU operations are performed only on registered data. So
operands are required in the register. After manipulation, the result is also
placed in a register. Here three address instruction formats are the compatible
instruction format.

. iii) Stack based CPU Organization

The computers which use Stack-based CPU Organization are based on a data
structure called a stack. The stack is a list of data words. It uses the Last In First
Out (LIFO) access method which is the most popular access method in most of the
CPU. A register is used to store the address of the topmost element of the stack
which is known as Stack pointer (SP). In this organization, ALU operations are
performed on stack data. It means both the operands are always required on the
stack. After manipulation, the result is placed in the stack.
The main two operations that are performed on the operators of the stack
are Push and Pop. These two operations are performed from one end only.
1. Push –
This operation results in inserting one operand at the top of the stack and it
decreases the stack pointer register. The format of the PUSH instruction is:
PUSH
It inserts the data word at a specified address to the top of the stack.
 2. Pop –
This operation results in deleting one operand from the top of the stack and
increasing the stack pointer register. The format of the POP instruction is:
POP
It deletes the data word at the top of the stack to the specified address.
The advantages of Stack-based CPU organization –
 Efficient computation of complex arithmetic expressions.
 Execution of instructions is fast because operand data are stored in consecutive
memory locations.
 The length of instruction is short as they do not have an address field.
The disadvantages of Stack-based CPU organization –
 The size of the program increases.
Note: Stack-based CPU organization uses zero address instruction.
Zero Address Instructions –
Address is stored in the opcode, in the zero address instruction. A stack based
organization uses zero address instruction.

1.9 Addressing Modes-

The different ways of specifying the location of an operand in an instruction are called as addressing
modes.

The term addressing modes refers to the way in which the operand of an instruction
is specified. The addressing mode specifies a rule for interpreting or modifying the
address field of the instruction before the operand is actually executed.

1. Implied Addressing Mode-

In this addressing mode,

 The definition of the instruction itself specify the operands implicitly.
 It is also called as implicit addressing mode.

Examples-

 The instruction “Complement Accumulator” is an implied mode instruction.

 In a stack organized computer, Zero Address Instructions are implied mode instructions.
(since operands are always implied to be present on the top of the stack)
 2. Immediate Addressing Mode-

In this addressing mode,

 The operand is specified in the instruction explicitly.
 Instead of address field, an operand field is present that contains the operand.

Examples-

 ADD 10 will increment the value stored in the accumulator by 10.

 MOV R #20 initializes register R to a constant value 20.

3. Direct Addressing Mode-

In this addressing mode,

 The address field of the instruction contains the effective address of the operand.
 Only one reference to memory is required to fetch the operand.
 It is also called as absolute addressing mode.
 Example-

 ADD X will increment the value stored in the accumulator by the value stored at memory location X.
AC ← AC + [X]

4. Indirect Addressing Mode-

In this addressing mode,

 The address field of the instruction specifies the address of memory location that contains the effective
address of the operand.
 Two references to memory are required to fetch the operand.
 Example-

 ADD X will increment the value stored in the accumulator by the value stored at memory location
specified by X.
AC ← AC + [[X]]

5. Register Direct Addressing Mode-

In this addressing mode,

 The operand is contained in a register set.
 The address field of the instruction refers to a CPU register that contains the operand.
 No reference to memory is required to fetch the operand.

Example-

 ADD R will increment the value stored in the accumulator by the content of register R.
AC ← AC + [R]

NOTE-

It is interesting to note-
 This addressing mode is similar to direct addressing mode.
 The only difference is address field of the instruction refers to a CPU register instead of main memory.

6. Register Indirect Addressing Mode-

In this addressing mode,

 The address field of the instruction refers to a CPU register that contains the effective address of the
operand.
 Only one reference to memory is required to fetch the operand.

Example-

 ADD R will increment the value stored in the accumulator by the content of memory location specified
in register R.
AC ← AC + [[R]]

NOTE-

It is interesting to note-
 This addressing mode is similar to indirect addressing mode.
 The only difference is address field of the instruction refers to a CPU register.
 7. Relative Addressing Mode-

In this addressing mode,

 Effective address of the operand is obtained by adding the content of program counter with the address
part of the instruction.

Effective Address

= Content of Program Counter + Address part of the instruction

NOTE-

 Program counter (PC) always contains the address of the next instruction to be executed.
 After fetching the address of the instruction, the value of program counter immediately increases.
 The value increases irrespective of whether the fetched instruction has completely executed or not.

8. Indexed Addressing Mode-

In this addressing mode,

 Effective address of the operand is obtained by adding the content of index register with the address
part of the instruction.

Effective Address

= Content of Index Register + Address part of the instruction

9. Base Register Addressing Mode-

In this addressing mode,

 Effective address of the operand is obtained by adding the content of base register with the address part
of the instruction.

Effective Address

= Content of Base Register + Address part of the instruction

 10. Auto-Increment Addressing Mode-

 This addressing mode is a special case of Register Indirect Addressing Mode where-

Effective Address of the Operand

= Content of Register

In this addressing mode,

 After accessing the operand, the content of the register is automatically incremented by step size ‘d’.
 Step size ‘d’ depends on the size of operand accessed.
 Only one reference to memory is required to fetch the operand.

Example-
 Assume operand size = 2 bytes.
Here,
 After fetching the operand 6B, the instruction register R AUTO will be automatically incremented by 2.
 Then, updated value of R AUTO will be 3300 + 2 = 3302.
 At memory address 3302, the next operand will be found.

NOTE-

In auto-increment addressing mode,

 First, the operand value is fetched.
 Then, the instruction register RAUTO value is incremented by step size ‘d’.

11. Auto-Decrement Addressing Mode-

 This addressing mode is again a special case of Register Indirect Addressing Mode where-

Effective Address of the Operand

= Content of Register – Step Size

In this addressing mode,

 First, the content of the register is decremented by step size ‘d’.
 Step size ‘d’ depends on the size of operand accessed.
 After decrementing, the operand is read.
 Only one reference to memory is required to fetch the operand.

Example-

Assume operand size = 2 bytes.

Here,
 First, the instruction register RAUTO will be decremented by 2.
 Then, updated value of R AUTO will be 3302 – 2 = 3300.
 At memory address 3300, the operand will be found.

NOTE-

In auto-decrement addressing mode,

 First, the instruction register RAUTO value is decremented by step size ‘d’.
 Then, the operand value is fetched.