{ GL. BAJAJ INSTITUTE OF TECHNOLOGY & MANAGEMENT GREATER NOIDA B.TECH ~ CSE Semester-II1) SESSIONAL TEST (ODD SEM 2021-22) Computer Organization and Architecture (KCS- 302 Faculty Name: : Dr. Lalit Tyagi, Dr, Sachin Yadav, Mr- Laxman Sasso be Vimal Singh, Mr. Rikendra Punia, Ms. Neha Jha tion: 02:00 Hrs Max. Marks: 50 (© Short answer type theoretical questions may be attempted in 150-200 words. The answer man te pre However, this rule is not applicable for numerical (Long answer type theoretical questions may be attempted in 260-300 words. The answers must be Precise. However, this rule is not applicable for numerical. (i) Mention Question number/section correctly. Numerical will be evaluated based on approach and step marking will be followed. Course Outcomes: = Following are the course outcomes of the subject:- 2 Code | Course Outcome (CO): Student will be able to Study of the basic structure and operation of a digital computer ACS-302.1 system. : Analysis of the design of arithmetic & logic unit and understanding. of the fixed point and floating-point arithmetic operations, | CS-3023 | Implementation of control unit techniques and the concept of a \ 13. Apply 2 Pipelining ss i Understanding the hierarchical memory system, cache memories 1L3- Apply KCS-302.4 |_and virtual memory. = Understanding the different ways of communicating with VO Lz ‘CS-302.5 | devices and standard /O interfaces Understand = Section: A | 1. Attempt all questions in brief. @xs1) | a. Solve the following of given binary number 02, K3 (10001101)2+(100110)2 — Ee (Explain the memory transfer operation in each case: i (i) R2 € M[AR] | (i) M [AR] € R3 - (ii) RS € MRS) ; = a ea es @ common bus system for 8 registers of 16 bts each. ‘The bus is constructed with multiplexers. co1,KI a. How many selection inputs are there in each multiplexer? b. What size of multiplexers en ‘ i ere in ? : s SF lie he fctons of vaos Tegisters- i) PC ii)IR ili) MDR ivJMAR Paw. = Show which method is best for multiplying 2 by 2 bits binary | “numbers with a help of diagram. C02, KI[2am four of the following pe rempt any four of the following ar [Solve X={A-B)*(C+D) using ) One address instruction ii) Zero address instruction con Ks oo a Z. Palin the TTcomputer with block diagram: 1% What i register? Define register transfer language, and desribe the register : transfer operation with suitable diagram. Sok ©. What is adder? Defi "7 iio E ee reuee fil adder and draw the logic diagram of al adder with [coum d_ Explain memory transfer with suitable transfer operations. a | ie “= Explain the Bus arbitration Method with suitable diagram. ae | co1,K2 a Section: C 3. Attempt any one questions (Marks 10x 1 = 10) “a. Demonstrate a Stack organization with the help of PUSH and POP nae Operations. ee b. Illustrate General register organization with the help of diagram having seven oe general register and design a control word for RI R2 + R3. | 2 4. Attempt any one questions (Marks 10 x 1= 10) E . : : 4. What is carry propagation delay? How the carry is propagated in carry- look ae ahead adder? Explain with suitable logic diagram of carry generation. 50 An Instruction is stored at location 300 with its address field at location 1. The address field has value 400. A processor register RI contains number 200. | Solve the effective address if the addressing mode is i)Direct ii) Immediate iti) aes | Register indirect iv) Index with RI as index v) Register direct. L Course Outcome Markswise | | BLOOMS LEVEL DISTRIBUTION = BLOOMS LEVEL O! Averivanie) (CHECKED BY HEAD OF THE DEPARTMENT