Theoretical Performance of the Capacitor—Diode Voltage Multiplier Fed by a Current Source Luigi Malesani, Senior Member, IEEE, and Roberto Piovan _Abuiract—In this paper theoretical performance of the CDVM, |s studed, with Impressed current input and. constant voltage ‘output. The operating modes of the CDVM are described, the expressions of the volages and currents are derived for the Incomplete configuration. The results are immediately extended to any input waveform. The case of sinusoldal current Input {ally characterized, giving useful design expressions. 1. Ixrropucrion |APACITOR-DIODE voltage multipliers (CDVM) have been used in several applications asa simple and reliable means to obtain a high de voltage from an ac source. Among the advantages offered by this solution isthe fact thatthe ac source voltage may be substantially lower than the wanted de voltage and that capacitor and diode ratings are lower 100,36 the sharing of voltage stresses is intrinsically ensured by the ‘multiplier operation (1]-15} ‘When a transformer is used as an 2¢ source for the mil: Liplier, substantial benefits in terms of voltage and insulation ratings of the transformer itself are obtained. Infact, the de voltage betwcen the primary and secondary winding can also bbe reduced, as compared with other solutions such as that of some seres-connected de supplies. ‘A number of modifications ofthe original Cockeroft-Walton circuit were propoted and applied, with substantial improve- ment of performance. These schemes, in most cases, were fed by low-frequency, low-impedance voltage sources. Ripple reduction and de voltage stresses were the major concem, 0 that in many instances, the fering action was entirely commited t0 one of the capacitor stacks included in the multiplier (7) ‘The CDYM advantages become particularly appreciable in those applications, such as space and communications, where small size and weight and high efficiency and reliability are of primary importance. In these cases, the main disadvantages of CDVM, ic, the delay between input and output and the nonneglgible amount of capacitance needed, ae reduced, within acceptable limits by the increase of the operating frequency of today's converters In resonant converters, which are used more and more owing to the advantages of efficiency and the effects of parasitic parameters they offer, the operating frequency is even higher. Manuscript ccved Mach 2,190; revied December 4 192 Eon! wah the Deparment of lei Engin, Univer of Bava 3131 Poe, ty Re Piovun Is with te ato Gas lonza, National Resch Cost (CNB) of Tay, 35131 Pass ly Fp |. Copstor-de voltage mate ‘Thus, the adoption of @ voltage muliplier (Fig. 1) with a resonant converter may tum out to be very convenient [6] [S. In fact, not only ean the multiplier response and size become quite good, but also the reduetion of the transformer ‘output voltage allows us to reduce the leakage inductance and the secondary parasitic capacitance which affect the resonant system operation “The design criteria and the operating conditions of a CDVM fed by a resonant converter may be much different from those csually assumed for these ciruits, which have been studied in the past mainly under the hypothesis of an ae voltage source atthe input and a resistive load atthe output [1}-{5] [At high frequency, the diode commutation transients affect, the behavior, and the ac curent stresses on capacitors become limiting factors. The adoption ofa series resonant converte. ‘operating above the resonance frequency. which often includes the transformer leakage inductance in the resonating induc- tance, may be convenient as it ensures a sinusoidal input current waveform, thus minimizing the commutation transients and the harmonic losses. At these frequencies, the multiplier capacitors become fairly small, and the output pple can be casily filtered by means of an additional capacitor connected to the output terminals. Thus, the simple Cockcroft-Walton circuit (Fig. 1, with a minimum component count, may be the most convenient choice Tn the presence of the output capacitor, there are some advantages in adopting. a multiplier configuration which can be called incomplete, where the upper capacitor Ci of the rounded stack is missing (Fig. 1). Indeed, less current ripple ues. 4099/9380300 © 1999 IEEis injected into the output through capacitor Cp, while the presence of the additional output capacitor reduces the need or the voltage filtering piven by the capacitors of the CDVM, ‘The behavior of the CDYM under the conditions outlined above is quite diferent from the classical one, better model should be that of a multiplier fed by a current soure, with the ‘output Kept at a constant voltage, Under these assumptions, {in this paper, the theory of operation of incomplete CDVM is developed. Input-output relations are obiained, and useful ‘design parameters are derived ‘An extension ofthe theory is also indicted forthe ase of ‘complete CDVM, 1, GeNeRa Hyporveses With reference to the general scheme of the CDVM shown in Fig, [the following hypotheses are assumed + ideal diodes, with no voltage drop, leakage current, ot ‘charge recovery ‘+ no snubber circuits in parallel 10 the diodes + ideal, lossless capacitors + equal capacitance value of all capacitors + impressed current atthe CDVM input 7 voltage atthe CDVM output 1 will also be assumed that there is one and only one steady-state solution corresponding to given input and output ‘According tothe above hypotheses, no resistive elements are included in the circuit. Thus, curreat and voltage transients, if any, are of infinitely shor duration, TL. IncowPueTe CDVM Tutory A. Square Wave Operation In order to study the steady-state behavior, an stage CDVM incomplete configuration is considered, where capac- itor Cay between the CDYM output By andthe top of the capacitor column B is missing (Fig. 1) In the fist instance, 3 square input current waveform is assumed, so that the injected charge is 8 Tinearfunetion of time, ‘Taking into account thatthe only de path berween ground and CDVM output is through the series of all CDVM diodes, and no de path exists between the input and the output [Fig 2a}. first statement is that in steady stat, all of the diodes carry the same charge in the period, ie. the same average Consider now the negative half wave of the input curren During the corresponding half period only D, diodes conduct ig. 2(6)]. These diodes have the eathode’on the column connected to the input (left-hand side in Figs. 1 and 2(b)) ‘As demonstrated in Appendix 1, the conduction takes place for one diode at atime, from top to bottom. Thus, each diode, when conducting, caries the whole input current ig. Ifthe output voltage £ is greater than a limit (see Appendix 2) which can be expressed as Vian = Kein LeT/C) o Ti, 2 SYM cet pa) Due pah pl mene Suligesd cendoton (Typed postive Tlf paid concn belte tia ah Type path hal fr comlcon shethen all D, diodes conduct during the negative half wave. ‘The conduction stars with diode D,yy and propagates orderly down to Dy (see Appendix 1), {As all diodes carry the same charge in the period 7. the ‘conduction period ofeach D, diode, for a square-wave current input, takes the same fraction 7'/2IV of the negative half period. It tums out that, if isthe half-wave average input ‘curten, the average curent flowing in each diode during the period Tis 1 lal(2N), @ [As suid befor, this is also the average current flowing in the output diode Day, as well in every Dy diode (Fig. 1). Inthe postive half period, there is a fist interval where the output diode Day is off, while the other Dy diodes conduct, fone at atime, starting from Day) [Fig, (6)]- At given instant tuy’,Day begins to conduet, and keeps conducting ‘ntl the end of the positive half period. This means that, after tuys there is one and only one other diode Dy conducting together with Day (Fig. 2()]. Thus, indicating by Dax the diode which is conducting when Dux tums on, afer instant tay, the diode Day continues to conduct uni (441) where diode Djg,x) begins to conduct. Later, diodes Dyy,1) ~Di conduct, one at time and together with Das, uni the end of the half perio, This behavior is qualitatively described in Fig. 5 (although this figure refers to a different input waveform). The conduction times dg: of Da: diodes, in the case of an input current square waveform, are Tunetions only of the period 7’ and ofthe numberof stages 1, and are independent Of current ,. The calculation of these values, as well a5 the demonstration of the above statements, are reported in [Appendix In particular, the index kof the diode De, which is conducting when Day is turned on, is obtained in (A6), and calculated values asa function of N aze given in Table I Given the sequence of conductions in both half periods, the current distribution in each time interval dy, and dy, is determined. From this, the behavior of voltages ve av and ves; (on capacitors Ca, and Cx, and hence of the node voltages, can be derived, This is particularly easy for a square-wave input current: indeed, in this instance, during time intervals diy oF dg; between transitions tof fy, when a diode tums fn and another tums off, not only the distribution, but also the values of the branch currents Keep constant. Thus, the voltages vay and vp, of nodes A, and B; vary Tinestly with time, giving piecewise voltage waveforms (Appendix 1). An ‘example is shovin in Fig, 3 for a five-stage CDVM and a large input curren To completely determine the voltage behavior, it must be taken imo account that, in seady state, the same current and voltage distribution epeats at each period, For this purpose, consider that, at the end of the negative half period, the voltages Vea: and Vopys-1) on capacitors C4; and Caii-1) are equal. Similarly, during the positive half period, at time ‘yg when a diode Dg, ceases conducting and the next diode Daj) stasts conducting, the voltages Veg, and VZip, 07 capacitors C4; and Cop; covinected to these diodes are equal ‘ee Figs. 1 and 2). Taking into account the current distribution, all ofthese voltages can be calculated asa function of voltages ig 3. COVA ne vhages with uae wane put Vas, 8 shovn in Appendix 2, thus obtaining a set of N ~ 2 equations (A13). These can be added to the condition that at the end of the postive half wave, the voliage of node Ay rust equal the output voltage F(A16). By solving the set of ‘equations (A13) and (A16) (see Appendix 2) voltages Vos are completely determined in closed form. For the sake of conciseness, the solution may be expressed in the form Voss = E/N + (InT/O)K2 8 Vea =Voau-r) + (aT /C)K, BsisM ® where Ki; is given by (Al4) and (AIS), which completely determines the unknowns. From capacitor voltage values Vas at the end of the negative half period (which ae also the values tthe beginning ofthe postive half period), and from curtent distributions and durations, the complete circuit behavior can be determined, In particular, the voltages Vai of nodes Ay atthe end of the negative half wave can be expressed in the normalized form Vis = Vail E peieny o From Figs. 1-3, its evident that, atthe end of the negative half wave, Vai = 0. Expressions similar to) ean be given forthe total capacitor voltage variations inthe period. These ae, by definition, the peak-to-peak ripple voltages Vz. and Vc. The variations are equal and opposite for capacitors Cy; and Cigs-1) andTABLE 1 Nove Vounce Comments Ky N33 4s 67 # # 0 08 om O78 11 <0 0827 130 1.86 013 0585 139 02 0483 28 26 ast hat ons 222 081 0918 TABLE It Cuscron Rime Comme 0555 OS 0400 047 1167 0280 0200 0333, 125 0200 020 2 Da 0357 ass 0450 5 0100 0167 0357 0395 0.399 040 2m 032 433 0214 0280 0278 m2 0101 os os are given in normalized form by La View Kei = Vecwiety Rsism EC © while for Vics, coeficient Kx equals 05. Coefficients; and K, re independent of [, and E. and ‘depend only on ‘and N. They are derived in Appendix 2 and the calculated values forthe most common configurations are reported in Tables 1 and Il. The knowledge of node voltages and of ripple on capacitors is of great inierest for the design of CDVM components. From the above treatment, it can be easily shown that the input voltage atthe node Ap has a normalized time behavior of the form alt] a ft Kanal] + Beko] where s4(t/T) isa square wave of amplitude 1 and period 7 and fy(t/T) is a piecewise function of period T and unitary amplitude depending only on 1V and on the normalized time Uff. Cocflcients Ks and Ki, depend only on 2 o B. Other Waveforms From the preceding theory, it results tha, under the idealized conditions assumed, the CDVM is charge-contrlled system whose behavior depends on the amount of the charge injected atthe input rather that on the time elapsed. ‘Thus, once the behavior with square-wave eurent input is {determined the operation with whatever waveform ofthe same period 7 can be obiained by a simple time transformation. If ‘is the time with the square wave, and ty. isthe time sith an input waveform igyo = Tu -WV(tu/T), the transformation is given by [O tanto = [ 1 Wonar where sa(r) is a unitary square wave, W(r) is a peritic function of maximum amplitude 1. and with the constraint that the total positive ad negative charges injected by the two waveforms must be equa With these constraints, the charges flowing in the vari- fous branches are the same. The beginning, the half, and the end of the period coincide. The corresponding voltages Veai.Vowi¥4e. Vai and also V2.4, and Vig, remain un changed and ate expressed by the same equations, Tn the case of a DCVM fed by a resonant convener, the input curent is sinusoidal. In this ease, the transformation of ® ° whose expression is valid within the fist period. ‘By means of this transformation, the node voltage behavior for sinusoidal input current hs been derived from that of Fig. 3 and is shown i Fig, 4. The eoresponding eurent waveforms Of Dy diodes inthe positive half period are shown in Fig. 5 An important figure for the CDVM is the input voltage ‘The firs-order components of that voltage are of particular relevance with a resonant converter which delivers a sinusoidal current to the CDVM. The analysis of the input voltage waveform, obtained {rom (7) by transformation of (9), gives normalized first-order components: Yin = Ka, fer = Kea(aT/BC) «10 where vj. isthe normalized peak value in phase withthe input ccurent and vs the coresponding. quadrature component Tris noticeable’ that the first depends only on XV, while the second depends on normalized curtent I, °/EC. Caleulaed values of Ky, and Ky are given in Table I ©. Saturated Operation By increasing the CDVM input curren above the limit given, bby (2, the condition that no D diodes conduct during thetnt Voetoe Cones a, Key: Loe Our Votsaae (Cosmet ‘Kiyo, Doce Dyy Tone -Ox Bea Noo 4 5s 6 7 #9 © Ka O22 0159 0127 106 GOT 0mm OTT a0 Hi 0682 OOK 116 Lad 145 150 2H 230 Fie 142271 436 633 ROSS M3177 bar ratio Heaters teedstecen tates Fg. $. Caen in does Dy isd! np, positive half wave is no longer met. During this perio, the ‘Byy-s) node voltage inreases so that eventually diode D. turns on. By further increasing I, (or decreasing E),Dy the other lower D, diodes also conduct in the post wave, Correspondingly, the output to input curent ratio Iola increases, up to 1/2 value when the output voltage Eis 20, ‘The analysis of the CDVM operation in these conditions is quite involved, and will not be reported here because this kind of operation is not usual and happens only in transient and fault conditions. lL 7 Fp & Noma ouput carer ess voip. The above analysis, however, has put in evidence thatthe ‘operation of the CDVM can be represented in a normalized form, depending only on the number of stages NV and the normalized mean current J,7/EC. Thus, by simulating the ‘operation of a CDVM for different choices of 1V and for 4 sufficient set of values of normalized current, & complete ‘description of the behavior of every CDYM in all conditions can be obtained In Fig. 6, the normalized output current Ip/Iy is given as 4 function of the reciprocal of the normalized input curent (which can be thought of as 2 normalized output voltage). From the figure its evident thatthe CDVM fe by «current source perfor like a current source, unless the output voltage goes down to the saturated operation. IV, Comptes CDVM OrzRarion ‘An analysis similar to that performed above also can be ‘made for the complete CDVM configuration. However, inthis case, such a detailed analysis is not needed to determine the steady-state voltage distribution and derive the main infor- mation on the external circuit behavior. Infact, due to the symmetries in the circuit, final voltages can be calculated by ‘means of charge lance calculation only, without taking into fccount the currents in the branches and their durations. This Approach is similar to that of the classi theory. developed for the multiplier fed by a voltage source [1], [5]. Only the results ofthis calculation will be summarized here. For this purpose, it can be stated first that, in both hal waves, the diode conduction starts atthe middle ofthe circuit and propagates either towards the top and towards the bottom, with two diodes conducting at atime. Thus, during the postive half period, the voltage of each node “Ay of the section enclosed between the conducting diodes is equal to that ofthe comesponding node B, and stays at the same value until theend of the half period, The same happens, during the negative half wave, for nodes A, and Bi. If the output volage is higher than Vasu = Ki(LoT/C) ay With Kj @ function of Vand calculated similarly 0K only Dy diodes conduct during the positive half wave and only D, diodes conduct during the negative half wave. Ths all diodes conduct the same average current, expressed by (2), Taking into account the resulting charges injected into capacitor terminals, and with the condition that the total voltage across the column B does not vary. the capacitor Voltage variations during the positive hall pe calculated as od can be Vea a, «3 Opposite variations occur. of course, during the negative half perio. ‘The above-mentioned relations among capacitor voltages can be expressed as aa) where Vz, and Vel, are the voiages on capacitors C4, and Coy atthe end of the postive half wave, and Vi-y, and Vy, ae the corresponding voltages atthe end of the negative half wave. The last equation takes into account that the total voltage in column # equals the total voluge E. From the foregoing equations, capacitor and node voltages are determined. In Particular. from (13), tbe sddtional charge ripple injected in the output with respect tothe incomplete configuration can be caleulated as og as) Sens Even in this ease, the time transformation of (8) can be applied for different waveforms, Also, forthe complete coafiguration, the behavior is charg controled and can he expressed in normalized form, dependin fon N and on the normalized current 1,/ EC V. EXPERIMENTAL EXAMPLE ‘Toconfirm the theoretical forecasts, an experimental CDVM. has been set up. with the following characters +10 nF capacitors +S RV output voltage + 100 mA average sinusoidal input current + frequency 20 kHz In Fig. 7, the node voltage behavior is shown, In Figs, 8 and 9, the curents in diodes D, and Dy are reported. The excellent agreement sith theory ts evident VL. Concwusions [In this paper, the theory of the incomplete capacitor-diode voltage multiplier (CDVM) has beea developed, under theconditions of impressed input current and constant output voltage. Twas demonstrated that, under these conditions, the CDVM, ‘operation is quite different from that described in the classical ‘ueatments. ‘A closed-form solution was derived, and useful design data were given, “The extension ofthe results to any input curent waveform ‘was performed. ‘Some indications were given about the extension of the ‘theory to the ease of complete CDVM. Vu. nthe negative half wave ofthe input current ig, one and only one D, diode conducts at a time (Figs. 1 and 2(b)) Th fact, f the input current has a square ‘waveform of amplitude [,, as the total curent carried by the diodes from the left side to the Fight side ofthe converter must equal the input current, thee is almost one negative diode conducting uring the negative half wave. ‘But in the incomplete CDVM, when one diode conducts during the negative half wave, no other diodes can be in conduction. In fact, the conducting diode, supposed idea makes a short between its terminals [Fig. (0), so that the par ofthe circuit above the conducting diode becomes completely floating, and no curent can low in the branches ofthat part (oF ‘course, output diode Dax cannot conduct during the negative half wave). Thus, not only can no other diodes conduct above the considered diode, but also none of them can become ‘conducting during the rest of the half wave, Moreover, since all diodes must conduet the same charge in the period, and since it has been assumed that no D, diodes conduct in the positive half wave, all of the D, diodes conduct during the negative half wave It follows that the conduction of the D, diodes stats at the beginning of the negative wave with Dax and involves, in succession, all D, diodes down to Day. All Dy: diodes conduct the current Ty for time dys, stating fron) ime ts ‘until fr) {See Figs. 1 and 2(0). All conduction times dy are equal 1o /2NV, so thatthe charge flowing in each diede is L61/2N, thus confirming (2. Inthe positive half wave, consider frst thatthe ourput diode ‘Day once starting to conduct, keeps conducting until the end ofthe half period. This follows from the fact that, a it is easily demonstrated, when there is a positive input curent entering the multiplier, all of the node voltages are rising or at least constant ‘Thus, a shown in Figs [and 2{¢), there is ime interval, at the beginning of the postive half period, where Day Is off. At time fg, it starts to conduct until the end ofthe half period. When Day is of, the situation is very similar to that fof the negative half wave, and only one positive diode can conduct at a time. starting ftom the highest Dacy—1)- The ‘Dai diodes conducting before tay carry a current [yy equal toy for a time dy, from ty 10 fay) (Fig. 3). Foe these diodes, to satisfy the charge condition of (2), all conduction imes da; are equal to 7/2N. APPENDIX. A Even when diode Djy is on, if there are no D, diodes ‘conducting, no more than one other Dy diode can be on (Fig. 2(@)]. Infact, if there were two Da diodes on, they would put in parallel the enclosed sections of capacitor columns A and B. Thus, in these sections the current in column A should be equal and withthe same direction as in columa I (see Figs. ‘Vand 2()]. But, as there is total current flowing toward the output and Day, the curent in column B would be flowing inthe upper direction and would cross the upper Dy diode in the forbidden versus. On the contrary, it can be concluded that there is no curent flowing in column B above the conducting ‘Dj diode, so that no other Dy diodes above the conducting fone can be tuned on (Fig. 22) “Taking into account that all Dg diodes must conduct in {he positive half period, also when Day is conducting, the conduction of the other Dy diodes is propagated from the top to the bottom, involving all diodes one ata time Let us indicate as Dy the diode whieh is conducting when, attime tg, diode Duy: begins to conduct. After ty, curent is shared between the conducting diode Dj; and the output Wxle Day. The sharing is determined by the equivalent impedance of the two paths [Fig. 2()], so thatthe current through Dy is Ta = IN ~9IN an and the current in Day’ in the same interval day (from ta; to tainty: Fig. 3) when Dg; conducts is Tayi = hil. way As the total charge flowing in each diode is 1,7'/2N, the corresponding conduction time a T/AN ~ i) “ varies with [As regards the conduction interval djs of diode Dax, it i vided in atime interval di, {om tue 10 tu, where Dux is off and the current in Duy is Iq, and in atime interval dj, from tay 10 tay, Whee the current is according to (Al). From the preceding equations, the total charge condition for diode Day can be expressed as ToT Taney So, tawcda = Fi ws fe [a re “-El-E gt} 4 Equation (AS) also determines the value of whichis the maximum for which a, > 0. Thus, «ao, “The total charge condition forthe diode Dae determines the time interval dy From (5), and taking into account that the‘curest in Da in this interval is Ia, results in TW ah wah VILL APPENDIX B. Voltages V4, are defined asthe voltages on capacitors Ca, a the instants tag.) when, during the positive half period, the diode Dy connected tothe upper terminal ofthe capacitor ‘ceases to conduct (Fig, 2(8)] For capacitors C4; above Dax, these voltages can be calculated taking into account that ia each C4, flows the charge conducted, up 10 fg:—1). by all of the Da diodes above it (ot including Day, which i of). Since in the diodes aboveDx the cument is I, for atime T/2N, it results in ie ve ot a Yeas =Veai~ 3 Thal BNC weisieN-1, ) Vea as) AA similar calculation ean be done for capacitors under Cay, including this one, but the different conduction times of| various diodes inclading Day) must be taken into account [Sea rea ban 5 «| ” sis k. : Vea =Voar— as) ‘Thus, from (A3), (AS), (AT), and (A9) for capacitors below Dan, it results in Vou =Veus- ae 2NC [w-ir9-E bsissl ‘aio, 1 shouldbe pointed out hat voltages V4, are defined for ifferent instants ta) (Fi. 3). Comesponding voltages VZp, on capacitors Cy in the same instants, can be calulated taking into account that ‘Da diodes carry the same charge, and that, according to ini Statements, at the end of the negative half period, voltages Varn = Vous (Fig. 26). Ths, Vows ION isis 1. ay Voltages on Cr, capacitors do not change until the end of the positive half wave, so that (AL) also gives the values of voltages Zp, atthe end of the positive half period ‘On the contrary, owing tothe conduction of Dw, there is «voltage variation on each eapacitor C's alter instant. -1) Capacitor voltages {atthe end of the positive half period can be derived from the same condition on the total charge carried by Dg diodes: ar, From (A11) and (A12), (6) and values of Ky; are derived immediatly AS Veg, and Véiyy must be equal, from (A9)-(A11) the following set of equations can be derived: Vea =Voauen + T/C). BsisN] (AI3) =(N =i n/N [er2sisN] (au _(QN-2: +3) 2 Fe psiseey] (as) Vest >, Vou =. (a6) Equation (A16) is the condition on the volage Vian: of node Ay atthe end of the positive half wave, and can be expressed from (AL!) and (A12). ‘The set of equations (A13)~(A16) can be solved, giving the set of equations (3) and (4), with i+) Sy pb grisea] w-o[- De +E aan} The voltage Vera: on capacitor Cas is determined directly by the input current behavior and the condition thatthe mean input voltage is zero. By adding recursively (3) and (4), (5) is obtained, where an Ky =D, Pty esisM, (als) Limit voltage Vin is found by the condition that, atthe end of the positive half period, the voltage of node By) is not higher than Eso that diode Dw doesnot condet TFig. 2) From (A11), @), (4), and (A18), we obtain Kian = N[Ky + (N ~1)/4h The values of Kim for the most common number of stages LN are reported in Table I (ang)REFERENCES TNT MM, Wins, “Anas of Cokeoh aon volage tips with {Babi ibe tps nS Inn a 2 £21 2S Enger “rental perma of wage mae 1 I Sa Cnn SEs pe DS TT 181 RAC Co aed race ven poe? pen fo ud leaden ct ASG, al pp. 1b a28 (a) E'e°schurs JB. Sn W. feet “An fit 60 igh ‘olga sulin EEE PES. py. 16-38 ts) PIMP Gavan LO Che Topolopal esr ad nso Yolige muller crn EEE Tans Chen nl CaS 2 patie on. or (6) BL hem. "Dior ar peste set ia behtesecy DOD comenen EEE Fo Power Elcom, wl he 00 Bp. para Ir) G04 See Hantok of Refer Crowes Cis: Wy, 198 {8h Eitan erate “Ams of fbi ocr el et ‘ane tage miter wih capcne up e P Ewpoon ‘Spe Pome Cn SPC’ Mai Sp O09. Lai Mates (65-5495) a am in Leni (Sica, aly 08 Sepueber I, 1838. He re owas. le be Unversity of Favs 82 ‘rom 1963401964 he vas supa a a searcher nthe Cato Gs lnizet of CNR, Fa TSet to 1979 he wae an Asan of lect Engen, an fm 1968 to 1978, a0 an AS tstne Prien of Eston Component a he Usierty of Padova, Since 17S he as heen 2 "Prieune of Applied Beconce the sae Universiy. His meres ie it power eke, ce Gig. lea ‘Mls member of he AEL Roberto Plran ws br in Megan S. Vile (Paton) ay in 1955, erected the Dr. pee {neki Cogicrng with boas, fen he Univesity of Pato 980 ‘Since 1900 he ae own wih th Iu Gat Anam of the Natona Recah Coan (CNR) Cem te plana pyc of RP an experimen ee tries ed on car nd le ‘cae eonvenc adh one an comput imwlion of eles slr an en stems