Johns Hopkins Engineering

Introduction to GPU Programming

Module 1 Lecture 1B CUDA Hardware part 1

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 Chancellor T. Pascale
Computer Science Department

Images from Wilt, CUDA Handbook Chapter 2

Overview

1. CPU Configurations

2. Integrated GPUs

3. Multiple GPUs

4. Address Spaces in CUDA

5. CPU/GPU Interactions

6. GPU Architecture

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1.1 CPU Configurations

The material in this video is subject to the copyright of the owners of the material and is being provided for educational purposes under
rules of fair use for registered students in this course only. No additional copies of the copyrighted work may be made or distributed.
1.1 CPU Configurations

Figure 2.1 CPU/GPU architecture simplified

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1.1.1 Front-Side Bus

Figure 2.2 CPU/GPU architecture - northbridge

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1.1.2 Symmetric Multiprocessors

Figure 2.3 Multiple CPUs (SMP configuration)

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1.1.3 Nonuniform Memory Access
Figure 2.4 CPU with integrated memory controller

Figure 2.5 Multiple CPUs (NUMA)

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1.1.3 Nonuniform Memory Access cont’d

Figure 2.6 Multiple CPUs (NUMA), multiple buses

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1.1.4 PCI Express Integration

Figure 2.7 Multiple CPU with integrated PCI Express

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1.2 Integrated GPUs

The material in this video is subject to the copyright of the owners of the material and is being provided for educational purposes under
rules of fair use for registered students in this course only. No additional copies of the copyrighted work may be made or distributed.
1.2 Integrated GPUs

Figure 2.8 Integrated GPU Figure 2.9 Integrated GPU with discrete GPU(s)
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1.3 Multiple GPUs

The material in this video is subject to the copyright of the owners of the material and is being provided for educational purposes under
rules of fair use for registered students in this course only. No additional copies of the copyrighted work may be made or distributed.
1.3 Multiple GPUs
Figure 2.10 GPUs in multiple slots
Figure 2.11 Multi-GPU board

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1.3 Multiple GPUs cont’d
Figure 2.12 Multi-GPU boards in multiple slots

Figure 2.13 Multi-GPU boards in multiple I/O

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