Amiga

A1200_R1
Rev.1.38 (06.09.2012)
 Revision History
REV DESCRIPTION DATE APRVL MANAGER
0 Engineering Prototype 03/13/92 GRR
1 Advance Engineering Release 06/29/92 GRR

Jumpers and Stuff Connectors 1a Pilot Production Release 09/09/92 GRR

1b FTZ Production Release 09/09/92 GRR
REF TYPE DESCRIPTION PAGE REF TYPE DESCRIPTION PAGE 1d FCC/FTZ Production Release 10/10/92 GRR

R246 SMT NTSC Color Burst 4 CN1 DB9P Mouse/Joystick 1 5

R202 SMT PAL Color Burst 4 CN2 DB9P Mouse/Joystick 2 5
R625 SMT Keyboard MPU Clock 9 CN3 RCA-J Right Audio Output 5
R624 SMT Keyboard/System Reset 9 CN4 RCA-J Left Audio Output 5
CN5 DB23S External Floppy 8
CN6 DB25P RS232 Serial Port 7
CN7 DB25S Parallel Printer Port 7
CN8 SQ DIN Power Supply Connector 13
CN9 DB23P Video Output 6
CN10 RCA-J Composite Video 4
CN11 DIL-34 Internal Floppy Signal 8
CN12 SIL-4 Internal Floppy Power 8
CN13 MEM-30 Keyboard Membrane 9
CN14 SIL-4 Internal Floppy Power 8
CN13 MEM-30 Keyboard Membrane 9
CN14 SIL-4 Keyboard Status LED's 9
CN15 PCMCIA PC"Memory Card" 11

P9 EDGE-80 Memory Bus Expansion 12

Signal Glossary
SIGNAL DESCRIPTION (AREA) PAGES SIGNAL DESCRIPTION (AREA) PAGES

28MHZ 28.63636 MHz Master Clock LPEN Light Pen Trigger (Joysticks)
7MHZ 7.15909 MHz Processor Clock MTR Motor On (Floppy)
A[23:1] Processor Address Bus (68000) MTR0 Motor On - Drive 0 (Floppy)
ACK Data Acknowledge (Parallel Port) M0V/M0H Mouse 0 Quadrature V/H (Joysticks)
AS Address Strobe (68000) M1V/M1H Mouse 1 Quadrature V/H (Joysticks)
AUDIN Audio Input (RS232 Port) OVL Overlay ROM over RAM
AUDOUT Audio Output (RS232 Jack) OVR Override System Decoding
BEER
BG
Bus Error (68000)
Bus Grant (68000)
PIXELSW
POT0X/0Y
Genlock Pixel Switch (Video)
Pot Lines 0 X/Y (Joysticks) Key Components
BGACK Bus Grant Acknowledge (68000) POT1X/1Y Pot Lines 1 X/Y (Joysticks)
BLISS Blitter Slowdown (Chips) POUT Paper Out (Parallel Port) REF CHIP DESCRIPTION PAGE
BLIT Chip Memory Access (Chips) PPD[7:0] Parallel Port Data (Parallel Port)
BR Bus Request (68000) RAMEN RAM Enable (Chips) U1 68000 68000 Processor 16MHz 2
BUSY Device Busy (Parallel Port) REGEN Chip Register Enable (Chips) U2 8374 Alice (AA Agnus) 2
CASL/U Column Address Strobe (DRAM) RAS0/1 Row Address Strobe (DRAM) U3 8364 Paula 5
CCK/CCKQ Color Clock / Quadrature (Chips) RDY Drive Ready (Floppy) U4 4203 Lisa (AA Denise) 4
CDAC 7.15909 MHz Quadrature Clock (Chips) RESET General Reset
CHNG Media Change (Floppy) RGA[8:1] Register Address Bus (Chips) U5 f023a AA Gayle (CBM ASIC) 2,8,11
CLKRD/WR Read-Time Clock Read / Write (RTC) R/G/B Red / Green / Blue (Video) U6 asst ROM 512Kx16, 150 nS 10
COMP Monochrome Composite Video (Video) RI Ring Indicate (RS232 Port) U7-8 8520 Amiga VIA, 1 MHz 7
CSYNC Composite Sync (Video) ROMEN ROM Enable (ROM) U10-11 28F10 Flash Memory 128Kx8 10
CTS Clear to Send (RS232 Port) RTS Request to Send (RS232 Port) U12 CXA1145 Sony Video Encoder 4
D[15:0] Processor Data Bus (68000) RST Processor Reset (68000) U13 68HC05 amiga Keyboard MPU 9
DIR Step Direction (Floppy) RXD Receive Data (RS232 Port) U49 PST518 Low Voltage Sense IC 9
DKRD Disk Read Data (Floppy) RW Processor Read/Write (68000) U15 LF347 BiMOS Op-Amp 5
DKWD Disk Write Data (Floppy) SEL Select (Parallel Port) TL084 BiCMOS Op-Amp alt
DKWE Disk Write Enable (Floppy) SEL[3:0] Drive Select (Floppy) U16-17 Asst DRAM 256Kx16, 80nS 3
DMAL Chip DMA Request Line (Chips) SIDE Side Select (Floppy) U18-19 Asst DRAM 256Kx16 Optional 3
DRA[8:0] DRAM Address Bus (DRAM) STEP Step In/Out Command (Floppy) U20 391??? Budgie (ASIC) 2
DRD[15:0] DRAM Data Bus (DRAM) TRK0 Track Zero Sense (Floppy) U28 1488 EIA Line Driver 7
DSR Data Set Ready (RS232 Port) TXD Transmit Data (RS232 Port) U29 1489 EIA Line Receiver 7
DTACK Data Transfer Acknowledge (68000) VMA Valid Memory Address (68000) U30 BT101 Triple 8-bit Video DAC 4
DTR Data Terminal Ready (RS232 Port) VPA Valid Peripheral Address (68000)
E Peripheral Enable Clock (68000) VSYNC Vertical Sync (Video)
EXTICK Expansion Present / RTC Tick WE Write Enable (DRAM) X1 OSC TTL 28.63636 MHz NTSC 2
FC[2:0] Function Code (68000) WPROT Write Protect Sense (Floppy) OSC TTL 28.37512 MHz PAL alt
FIRE0/1 Fire Button 0/1 (Joysticks) XCLK External Genlock Clock (Video) Y451 XTAL 4.43619MHz PAL Burst 4
HLT Processor Halt (68000) XCLKEN External Clock Enable (Video) Y621 XTAL 3MHz Ceramic Resonator 9
HSYNC Horizontal Sync (Video) XRDY External Data Ready
INDEX Index Pulse (Floppy) X2 asst PAL Video Modulator 4
INT[2,3,6] Interrupt Request (Chips) asst NTSC Video Modulator 4
IORESET I/O Reset
IPL[2:0] Interrupt Priority Level (68000) ** Credit Card and IDE Stuff? **
KBCLOCK Keyboard Clock (Keyboard)
KBDATA Keyboard Data (Keyboard)
KBRESET Keyboard Reset (Keyboard)
LDS/UDS Upper / Lower Data Strobes (68000)
LED Power On LED / Audio Filter Disable
LEFT/RIGHT Left Right Audio (Audio)

DIRECTORIES AND REVISION HISTORY

DESIGN BY: DATE
c 1992 Commodore Business Machines G. Robbins 03/13/92 Commodore
Information contained herein is the unpublished, DRAW: GRR 03/13/92
confidential and trade secret property of LAST: GRR 09/09/92 Schematic A1200 R1d
Rev.1.38 (06.09.2012)

Commodore Business Machines, Inc. Any use, CHKD: C/A1200 Main Board

A1200 Rev 1->1d PCB

reproduction or disclosure of this information APPR:
without the prior written permission of USED ON NEXT ASSY
"Channel Z"
Commodore is strictly prohibited. SIZE REV

C.A.D. Generated
C/A1200 364718
C 364717 1a
SCALE SHEET 1 OF 13
No manual changes may be made to this document
PATH: /project/a300/channel_z.rev1 sheet1
© rebuild for www.amigawiki.org · for private use only
 VCC VCC

Channel Z
E133
U20
97 XCLK C28MHz 95
XCLK 1
2
2
1
28MHz

14

14

14

14

20
E124 68
98 *
_XCLKEN XCLKEN_
CCK_4 35 CC@4

Vcc1

Vcc1

Vcc1

Vcc1

Vcc1

2
1 2
XC1 XC2 XC3 XC9
XU1 XU2 XU3 U26X XU9 E131 68 2 1 22pF
0.047uF 0.047uF 0.047uF 0.22uF X1 OUT
3 1 2 94 OSC

7 Gnd1

7 Gnd1

7 Gnd1

7 Gnd1

10 Gnd1
CCK 36

10/10/92
2 1

1
28.63636MHz 68 *
BUDGIE E121

1
470 CPUCLK 90
OSCILLATOR 1 2
CPUCLK
R100 E122 27 2 1 *
391425 1 2
CPUCLK_A

2
CDAC_ 91 27 2 1 *
VCC
Note: PAL uses 28.37516 MHz C7MHz 92 E126
D(31:0) CLOCK PART 1 2
CCK_A
E128 27 2 1 22pF
1 2
CCKQ_A
A(23:0) 27 2 1 22pF
38 E123
7MHz
1 2 NC 7MHz
FC(2:0) E125 27 2 1 22pF*
37
_CDAC
1 2 NC _CDAC
27 22pF

U2
E127
2 1
20 35 40
A20 CCK
1 2
CCK

OOPS!
19 59 27 22pF
E129
2 1
A19
18 77 39
A18 CCKQ
1 2
CCKQ
U1
17 76 A17 27 2 1 22pF
FC2 12 2 16 75 A16
FC1 11 1 15 74 A15 SCLK
34 SCLK
FC0 10 0 14 73 A14
13 72 A13 14MHz
36 14MHz
15 _CDIS All this stuff serves to correct one minor Gayle bug 12 71
_CDIS 11 70
A12
and a number of Alice deficiencies not yet corrected. A11
10 69 A10 _LPEN
78 _FIRE1
A23 97 23 9 68 A9
A22 96 22 Assuming the changes are implemented in the production 8 67 81
_BOSS A21 95 21 Gaule chip, then all this sillyness is best erased... 7 66
A8 _HSYNC _HSYNC
A7
1 _BR A20 94 20 6 65 79
_VSYNC
_BR A19 93 19 5 64
A6 _VSYNC
A5
_BG 2 _BG A18 92 18 Reference Old Gayle New Gayle 4 63 A4 _CSYNC
80
_CSYNC
A17 91 17 =========== ========== =========== 3 62 A3
A16 88 16 2 61 A2
A15 87 15 XU1 74F74 none 1 60 A1 DMAL
18 DMAL
A14 86 14
_IPL(2:0) A13 85 13 XU2 74F02 none _INTR
17 _INT3
A12 84 12
2 67 _IPL2
A11
A10
83
82
11
10
XU3 74F74 none
8374 _NTSC
41 _NTSC
U26X 74F86 none
ALICE
1 66 _IPL1 A9 81 9
65 _IPL0 A8 80
0
MC68EC020 A7 78
8
7 XJ4 0 Ohm out
_RAS
57
_RAS
A6 77 6 _CAS
54
_CAS
A5 76 5
A4 75 4 XJ1 out 0 Ohm _WE
21
_DWE
A3 74 3
A2 73 2 XJ2 out 0 Ohm
5 CLK A1 98 1 26
CPUCLK A0 99 0 XJ3 out 0 Ohm
RGA8
27 8
RGA7
RGA6
28 7
U26 note 74LS86 RGA5
29 6

XU9
D31 27 31 RGA4
30 5
D30 28 30 RGA3
31 4 VCC
D29 29 29 RGA2
32 3
D28 30 28 VCC XJ4 33 2 XR9

2
RGA1
D27 31 27 1 1K
D26 32 26 1 2 16R4

2
D25 33 25 R591 11 _EN

1
16 _AVEC D24 34 24 1K * 56 1 CLK
_AVEC D23 35 23
DRA9
51 9 CPUCLK 19
10 74LS86
P19 _RST

1
DRA8
19 _BEER D22 36 22 50 8 2 18
_BEER D21 37 21 _FPU_SENSE 8
DRA7
49 7 _AS 3
P2 P18
17 NC
17 _DSACK0 D20 38 20 9 _FPU_MUSH DRA6
48 6 _ROMEN 4
P3 P17
16 NC
_DSACK_0 D19 39 19 _INT3 DRA5
47 5 FC(1) 5
P4
P5
P16
P15 15
DRA4 FC(0) XRDY
_DSACK_1 18 _DSACK1 D18
D17
40
41
18
17
U26 DRA3
46
45
4
3 A(17)
6
7
P6
P7
P14
P13
14 NC
13
D16 42
DRA2
44 A(16) 8 12 _AVEC
16 2 P8 P12 _DSACK_0
9 _RMC D15 45 15
DRA1
43 1 _DSACK_1 1 2 9
_RMC D14 46 14
DRA0
0 XJ9 0
P9

25 R_W D13 47 13
R_W D12 48 12 XU3 83
DRD15
_AS 23 _AS D11
D10
49
50
11
10 9
74F02
XU2 VCC DRD14
84
1
31
30
74F74 DRD13

10
24 _DS D9 51 10 11 2
_DS D8 53
9
8 8 13 12 9
DRD12
3
29
28 OOPS! - 32-bit / slow ROM

_S
D Q NC DRD11
13 SIZE0 D7 54 7 12 4 27
SIZE_0 DRD10

14 SIZE1
D6
D5
55
56
6
5
XU2 74F02 DRD9
5
6
26
25 XJ9 in - add ROM wait
SIZE_1 D4 60 4 11 CLK 8
DRD8
7 24
D3 61 CCK _Q DRD7
8

13 _C
3 DRD6 23
6 _RESET D2 62

1
2 22 9 22
_RST R_W DRD5

22 _HALT
D1
D0
63
64
1
0 VCC
XJ2 DRD4
10
11
21
20
_HLT * DRD3 RGA(8:1)

2
16 _RESET DRD2
12 19
DRD1
13 18
DRD0
14 17 DRA(10:0)
16
_INT3
XU3

_RAMEN

_REGEN
XU2 U26X

_BLS

_DBR
VCC 74F74
VCC DRD(31:0)

4
5 74F02 10

25
23

19

20
22 4 4 2 5 2 8

_S
A4 D Q
6 1 9

U0
A3 23 3 _RAMEN
4 24 2 3
_FPU_SENSE _SENSE A2 74F02

1
25 1 74LS86
A1 _REGEN
A0 26
CCK 3 CLK _C
_Q 6 XU2 XJ3
VCC _BLS

2
D31 33 31 *
1

18 _SIZE D30 34 30
D29 35 29 VCC
D28 36 28 _DBR
_FPU_CS 29 _CS
MC68881 D27
D26
37
38
27
26 1 2
E114
_OEB
D25 39 25 68 2 1 22pF

32
31

30

29

28
D24 40 24
D23 42 23
44 22

_RAMEN
_REGEN

_BLS

_DBR

_OEB
D22
31 _DSACK0 D21 45 21 31 54 D15 22
46 20 30 55 C14M
D20 D14
32 _DSACK1 D19 47 19 29 56 D13 23
48 18 28 57 CCK
D18 D12

U5
D17 49 17 27 58 D11
28 R_W D16 50 16 26 59 D10 _SENSE 64 _FPU_MUSH
D15 54 15 25 60 D9
21 _AS D14 55 14 VCC 24 61 D8 _FPU_CS 65 _FPU_CS
4

D13 56 13
20 57 12 2 5
_S

_DS D12 D Q
D11 58 11 23 53 A23 _WIDE 68 _WIDE
59 10 22 52
D10
60 9 21 51
A22
21 E113
D9
62 8 3 CLK 6 20 50
A21 _ROMEN 1 2
_ROMEN
D8 _Q NC A20 68 2 1 22pF
64 49 11
_C

D7 7 19 A19 _FLASH _FLASH

D6 65 6 74F74 18 48 A18
XU1
1

66 5 17 47
10

D5 A17
13 _RESET D4 67
68
4
3 12
74F74
9
16
15
46
44
A16 4145f023a _RTC_CS 17
_RTC_CS
_S

D3 D Q A15
11 CLK 1 2 14 43 16
D2 A14 _NET_CS _NET_CS
D1 2 1 XU1 13 42 A13
D0 3 0
11 CLK
_Q 8 NC
12 41 A12
AA_GAYLE _SPARE_CS 15
_SPARE_CS
_C

1 69 FC1 74
_EVEN_CIA _EVEN_CIA
13

0 70 FC0
VCC 73
34 _DS
_ODD_CIA _ODD_CIA
E112
E 10 1 2
E
1 2 33 _AS 68 2 1 22pF
XJ1 * 36 R_W _KBRESET 63 _KB_RESET
1 2 35 _DSACK1
68 R113 _OVR 26 _OVR
1 2 37 _DSACK0
68 R115 XRDY 25 XRDY
1 2 82 _BEER
27 R114 _BG 38 _ZORRO
1 2 39 _HLT
27 R117 PROCESSOR AND OTHER USEFUL COMPONENTS
40 _RST CONTROL FUNCTIONS DESIGN BY: DATE
27
1 2
R116
c 1991 Commodore Business Machines G. Robbins 03/13/92 Commodore
Information contained herein is the unpublished, DRAW: GRR 03/13/92
1 2 confidential and trade secret property of LAST: GRR 09/09/92 Schematic A1200 R1d
Rev.1.38 (06.09.2012)

* R118 Commodore Business Machines, Inc. Any use, CHKD: C/A1200 Main Board
1

reproduction or disclosure of this information APPR:

"Channel Z"
R594 without the prior written permission of USED ON NEXT ASSY
Note: Various components are for EMI Control
A1200 Rev 1->1d PCB
Commodore is strictly prohibited. SIZE REV
* C/A1200 364718
C 364717 1a
2

and may be loaded with funny things... C.A.D. Generated SCALE SHEET 2 OF 13
No manual changes may be made to this document
PATH: /project/a300/channel_z.rev1 sheet2
© rebuild for www.amigawiki.org · for private use only
 DRD(31:0)

31
30
29
28
27
26
25
24

23
22
21
20
19
18
17
16

15
14
13
12
11
10
9
8

7
6
5
4
3
2
1
0
DRA(9:0) BDRA(8:0)

NC

NC

NC

NC
39
38
37
36
34
33
32
31

10

39
38
37
36
34
33
32
31

10
12

11

12

11
9
8
7
5
4
3
2

9
8
7
5
4
3
2
1 1 2 0
68

P1

D15
D14
D13
D12
D11
D10
D9
D8

P0

D7
D6
D5
D4
D3
D2
D1
D0

P1

D15
D14
D13
D12
D11
D10
D9
D8

P0

D7
D6
D5
D4
D3
D2
D1
D0
R151A
2 1 2 1
68 R151B
3 1 2 2 0 16 A0
16 A0

U16 U17
68 R151C 1 17 A1
17 A1
4 1 2 3 2 18 A2
18 A2
68 R151D 3 19 A3
19 A3
5 1 2 4 4 22 A4
22 A4
68 R151E 5 23 A5
23 A5
6 1 2 5 6 24 A6
24 A6
68 R151F 7 25 A7
25 A7

DRAM
7 1 2 6 8 26 A8
26 A8
68 R151G NC 15 nc1 NC 15 nc1
8 1 2 7
68 R151H
9 1 2 8 NC 30 nc0 NC 30 nc0
68 R151I
29 _LCAS
29 _LCAS

28 _UCAS
28 _UCAS

14 _RAS
14 _RAS

13 _WE
13 _WE

27 _OE
256Kx16 27 _OE
256Kx16

U18-19 Optional

NC

NC

NC

NC
12
39
38
37
36
34
33
32
31
11
10

12
39
38
37
36
34
33
32
31
11
10
9
8
7
5
4
3
2

9
8
7
5
4
3
2
P1

D15
D14
D13
D12
D11
D10
D9
D8

P0

D7
D6
D5
D4
D3
D2
D1
D0

P1

D15
D14
D13
D12
D11
D10
D9
D8

P0

D7
D6
D5
D4
D3
D2
D1
D0
D(31:0) 0 16 16
A0 A0

U18 U19
1 17 A1
17 A1
31 102 D(31) DRD(31) 71 31 2 18 A2
18 A2
30 103 D(30) DRD(30) 70 30 3 19 A3
19 A3
29 104 69 29 4 22 OPT 22 OPT

U20
D(29) DRD(29) A4 A4
28 105 D(28) DRD(28) 68 28 5 23 A5
23 A5
27 106 D(27) DRD(27) 67 27 6 24 A6
24 A6
26 108 D(26) DRD(26) 66 26 7 25 A7
25 A7
25 109 D(25) DRD(25) 64 25 8 26 A8
26 A8
24 110 D(24) DRD(24) 63 24 NC 15 nc1 NC 15 nc1
23 111 D(23) DRD(23) 62 23
22 112 D(22) DRD(22) 61 22
21 113 D(21) DRD(21) 60 21 NC 30 nc0 NC 30 nc0
20 114 D(20) DRD(20) 59 20
19 115 D(19) DRD(19) 58 19 29 _LCAS
29 _LCAS
18 116 D(18) DRD(18) 57 18
17 117 D(17) DRD(17) 56 17 28 _UCAS
28 _UCAS
16 118 D(16) DRD(16) 55 16
14 _RAS
14 _RAS
15 120 D(15) DRD(15) 53 15
14 121 D(14) DRD(14) 52 14 13 _WE
13 _WE
13 122 51 13
12 123
D(13)
D(12)
DRD(13)
DRD(12) 50 12 27 _OE
256Kx16 27 _OE
256Kx16
11 124 D(11) DRD(11) 49 11
10 125 D(10) DRD(10) 48 10
9 126 D(9) DRD(9) 47 9
8 127 D(8) DRD(8) 46 8
7 2 D(7) DRD(7) 44 7
6 3 D(6) DRD(6) 43 6
5 4 D(5) DRD(5) 42 5
4 5 D(4) DRD(4) 41 4
3 6 D(3) DRD(3) 40 3
2 7 39 2
391425
D(2) DRD(2)
1 8 D(1) DRD(1) 38 1
0 9 D(0) DRD(0) 37 0

0 29 DRA(0)
BUDGIE 27
_ROE

28
RAS_1_ 1
68
2
_BRAS(1)
_RAS RAS_
26
R152A
24
RAS_0_ 1
68
2
_BRAS(0)
_CAS CAS_ R152B
31 23
_DWE WE_ CAS_UU_ 1
68
2
_BCAS_UU
R152C
34 22 1 2
_BCAS_UM
_DBR DBR_ CAS_UM_
68 R152D
21
14 A(1)
CAS_LM_ 1
68
2
_BCAS_LM
A(1) 20
R152E
15 A(0)
CAS_LL_ 1
68
2
_BCAS_LL
A(0) R152F
16 SIZE_1 30 1 2
_BWE
SIZE_1 BWE_
68 R152G
17 SIZE_0
SIZE_0 19
18 R_W
CAS_XX_ 1
27
2
_BCAS_XX
R_W R162
13
_DS

1
DS_ C152A C152B C152C C152D C152E C152F
470
UDS_ 11 1 2
_UDS R161
101 22pF 22pF 22pF 22pF 22pF 22pF
27
_OEB R163

2
OEB_
LDS_ 12 1 2
_LDS
27 R164
93
_RST RESET_

BRIDGE/DRAM PART

U18-19 Optional
VCC
20

20

20

20
1
6

1
6

1
6

1
6
Vcc1

Vcc2

Vcc3

Vcc1

Vcc2

Vcc3

Vcc1

Vcc2

Vcc3

Vcc1

Vcc2

Vcc3
2

2
C16A C16B C17A C17B C18A C18B C19A C19B
U16 U17 U18 U19
0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF 0.22uF
OPT OPT
1

1
OPT OPT OPT OPT
Gnd1

Gnd2

Gnd3

Gnd1

Gnd2

Gnd3

Gnd1

Gnd2

Gnd3

Gnd1

Gnd2

Gnd3
MEMORY AND...WELL, I USED TO REMEMBER
21
35
40

21
35
40

21
35
40

21
35
40
DESIGN BY: DATE
c 1991 Commodore Business Machines G. Robbins 03/13/92 Commodore
Information contained herein is the unpublished, DRAW: GRR 03/13/92
confidential and trade secret property of LAST: GRR 09/09/92 Schematic A1200 R1d
Rev.1.38 (06.09.2012)

DECOUPLING DECOUPLING C/A1200 Main Board

Commodore Business Machines, Inc. Any use, CHKD:

A1200 Rev 1->1d PCB

reproduction or disclosure of this information APPR:
without the prior written permission of USED ON NEXT ASSY
"Channel Z"
Commodore is strictly prohibited. SIZE REV

C.A.D. Generated
C/A1200 315718
C 364717 1a
SCALE SHEET 3 OF 13
No manual changes may be made to this document
PATH: /project/a300/channel_z.rev1 sheet3
© rebuild for www.amigawiki.org · for private use only
 2 1A1 1Y1 18 _RESET
4 1A2 1Y2 16 CCK_B
6 1A3 1Y3 14 _CSYNC_B
_CSYNC
8 1A4 1Y4 12 PIXELSW
74HCT244
11 2A1 2Y1 9 DR
13 2A2 2Y2 7 DG
15 2A3 2Y3 5 DB
17 2A4 2Y4 3 DI

_2G

_1G
+VID

U32

2
19

1
R233D R233C R233B R233A
RGA(8:1) 470 470 470 470
R264

1
U4
8 12 1N914 1N914 1N914

3
RGA8
7 13 RGA7 ZD
28
6 14 1
5 15
RGA6 682
R261 D231A D232A D233A

1
RGA5
4 16 RGA4 R7
57 35 R7 R232A

U30
3 17 55 1 2 36 26
2 18
RGA3 R6
54 3 4 37
R6 IOR
1 2
AR
RGA2 R5 R5
1 19 RGA1 R4
52 5 6 38 R4 24.9
51 7 8 11
DRD(31:0) R3
50 9 10 10
R3
25
R232B
R2
49 11 12 9
R2 IOG
1 2
AG
R1 R1
31 59 D31 R0
48 13 14 8 R0 24.9
30 60 15 16
R232C
29 61
D30 68 27
28 62
D29
47 R262 31
IOB
1 2
AB
D28 G7 G7
27 63 D27 G6
46 1 2 32 G6 24.9
26 64 45 3 4 33 1N914 1N914 1N914

2
D26 G5 G5
25 65 D25 G4
44 5 6 34 G4 ISYNC
24 +VID R231C R231B R231A
24 66 42 15
BT101
D24 G3
7 8
G3 49.9 49.9 49.9
23 67 41 9 10 14 D231B D232B D233B
LISA

1
D23 G2 G2
22 68 D22 G1
40 11 12 13 G1
21 69 39 13 14 12 C215 C216

1
D21 G0 G0
20 70
VIDEO DAC R215
15 16

19 71
D20 27 1K
D19 R263
4203
18 72 38 39 0.1uF 0.01uF VIDEO VIDEO

2
D18 B7 B7
17 73 D17 B6
37 1 2 40 B6
16 74 D16 B5
36 3 4 41 B5
35 5 6 42 C221 C222

2
B4 B4
15 75 D15 B3
34 7 8 6 B3
R216
76 32 5 18 NC
14 D14 B2
9 10
B2 VREF 15 1 2 1 2
13 77 31 11 12 4 0.1uF 0.1uF

1
D13 B1 B1
12 78 29 13 14 3 17 321

1
D12 B0 B0 COMP
11 79 15 16 R223
10 80
D11 27 74F139 19 BPF 787/620
D10 FS_ADJUST
9 81 12 30

2
R265

2
82
D9 _0 _BLANK
VVref
8 D215 4 5
D8
LM385
7 84 27 14 A0 11
Z221 6

8
2
D7 BLANK _1 R217
6 D6
1
682
5 3 13 A1 10 NC 29 470
VIDEO

1
4
D5 _2 _SYNC
1.2V 820
4

4
D4
3 5 9 NC R224
D3 _3

_EN
2 6 16

1 3

2
D2 REF_WHITE
1 7 D1
7 CLOCK
VIDEO

0 8 D215A

15
D0 NC NC NC NC NC

11 U23 VIDEO
415 8 910 31415

VIDEO DAC
NC WIDE

9 DELAY LINE
_BCAS_XX _CAS

74F139 2 6 13 11 18 16
24 7 12 17
_RST _RST
4

COMPOSITE

2
_0 R221 R222
10 2 A0 5 1K/820 1K
CCK CCK _1 NC
R225
Z222

1
20 26 3 A1 6
MDAT MDAT SOG _2 VIDEO 1 2
_MLD E375 2 1 21 58 NC
7 NC
*
_MLD _BURST _3

1 _EN
22pf 1 2
68

15

16

18

17
E376

CHROMA_OUT

LUMA_OUT

LUMA_IN

CHROMA_IN
SCLK
U23
2 1 22 SCLK
E377 22pf 1 2
271
14MHz 2 23 C14O
22pf 1 2
27 43
E132 C211
2 R_IN 23

U12
1 2 NC
C28O R_OUT
25 1 2
28MHz C28M
68
2 1
* 0.22uF
C212
3 G_IN CXA1145 G_OUT
22 NC

ENCODER COLOR
1 2
0.22uF
C213
4 B_IN 21 NC
CN10
B_OUT
1 2
0.22uF R234D
C237 E231

+
-
CV_OUT
20 1
FB
2 2 SIGNAL

1 2 1 2 2 1
75 100 100pF
470uF 3 SHIELD

C236 R235 RCA JACK

+
-
10 CS_IN CS_OUT
11 NC 1 SHORTBAR

1 2 1 2
360 VIDEO
100uF

2
R232E
75

1
R237
C214 10uF C235 VIDEO

+
-

-
8 AUDIO_IN 9
MONO 1 2
AUDIO_OUT
1 2 1 2

NTSC_PAL
100

XO_OUT
100uF

XO_IN
+VID

Vref

Iref

2
+VID R238
7 6 5 *

14

13
R209 ADDED REV 1B PCB

1
4.7K

1
1K R204 VVref
R202
MODULATOR

2
VIDEO

2
3
R209 Q201 C459 R459 C460 C461

2
_NTSC 1
+ +

1
1 2
10K
2N3904 *
R205 X2
- -

1
R246 2 22uF 27K * 1000pF

2
0/*
CCKQ_A 1 2 R203

1
VIDEO
2.7K/* VIDEO X2B RF OUT
1 1 AUDIO
VIDEO
+VID
2 2

PAL ONLY
VIDEO VIDEO
0.22uF E232

2
+VID
47pF*
1 2 3 3 +5
HI/LO
Y452 4.7
2 1

* MHz
0.01uF 4 4

1
2
C246 GND
C247 100uF +
1

2
1K
+VID 360/120
R236
5 5 TUNE
R244 1 2
6 6
R243 R245 VIDEO VIDEO
C239 - 7 MODULATOR
2

1
1

1
R241 4.33619MHz 1 2
R247
1 2
10K
4.7K */2.7K 15K*
Y451 3 C245 M/N-PAL OPTION VIDEO VIDEO VIDEO VIDEO
1
2

2
C242 C244 Q461
CC@4 1 ADDED REV 1E PCB
1 2 1 2 1 2 2N3904 56pF
2

VIDEO
15pF 3 0.01uF 2
C241
1

6.8K DENISE IS PRETTY MUCH INTO VIDEO...

1

C243 L241
1

VIDEO DESIGN BY: DATE

56pF VIDEO
1.2uH
R242 c 1991 Commodore Business Machines G. Robbins 03/13/92 Commodore
2

VIDEO Information contained herein is the unpublished, DRAW: GRR 03/13/92

1000pF Schematic A1200 R1d
2

confidential and trade secret property of LAST: BAF 2/24/93

Rev.1.38 (06.09.2012)

Commodore Business Machines, Inc. Any use, CHKD: C/A1200 Main Board

A1200 Rev 1->1d PCB

reproduction or disclosure of this information APPR:
VIDEO without the prior written permission of USED ON NEXT ASSY
"Channel Z"
Commodore is strictly prohibited. SIZE REV
VIDEO
VIDEO
Note: Components designated as Exxx may be loaded
C.A.D. Generated
C/A1200 364718
C 364717 1a
with EMI fliters, ferrite beads or resistors! No manual changes may be made to this document
SCALE SHEET 4 OF 13
PATH: /project/a300/channel_z.rev1 sheet4
© rebuild for www.amigawiki.org · for private use only
 MOUSE/JOYSTICK PORTS
VCC LEFT JOY
VCC
R370
CN1

1
4.7
DB9P CN1A 4.7K

1
R352
11 2 1 E355

2
E3511 6
6 6800pF 68
_FIRE0 2 1 1 2
68 470pF 2 22 E356

2
4
3
5
6
9
7
8
2 1 2 1

4
7
7

8
8
33
44
3
5
6800pF

6800pF
1
2
1
2

2
68
1
68
E357
U34
POT0Y E3531
6
9
9 6800pF
2 1
68
E358
2 7 1 2

POT0X 68 2 1 470pF 8 55
E3541 2A
2
SI 1
68 2 1 470pF 9
C352 3B

2
NC
10
74LS166
0.22uF 4C

1
5D

10 E E3741
QH 13 2
MDAT
68 2 1 470pF
11 F
S_L 15 _MLD
VCC
RIGHT JOY
12 G CLK 7 CCK_A
CN2 14 H CK_I 6

1
4.7

CLR
R362
DB9P
11 2 1 E365

2
E3611 6
6 6800pF 68
_FIRE1

9
2 1 2

P0Y 36 68 2 1 470pF 22 2 1 E366

U3
7
7 6800pF 1 2 68
P0X 35 33 2 1 E367
_RESET
8
8 6800pF 1 2 68
POT1Y 44 2 1 E368
E3631
_IPL(2:0) P1Y 39 2 9
9 6800pF 1 2 68
POT1X 68 2 1 470pF 55
E3641
P1X 38 2
2 15 _IPL2 68 2 1 470pF
1 14 C312 C311 C314 C313 C362

2
_IPL1
0 13 _IPL0
0.047uF 0.047uF 0.047uF 0.047uF 0.22uF

1
AUDIO

PAULA

DRD(31:0)
31 45 DRD15
30
29
46
48
DRD14
DRD13
8364
28 49 DRD12
27 50 DRD11 _INT6 21 _INT6
26 51 DRD10
25 52 DRD9 _INT3 20 _INT3
24 1 DRD8
23 2 DRD7 _INT2 19 _INT2
22 3 DRD6
21 4 DRD5
20 5 DRD4
19 6 DRD3
18 7 DRD2 R329
17 9 44 _RxD 1 2
16 10
DRD1 _RxD NOISE 10K
DRD0
_TXD 43 _TxD R339 C331
1 2 1 2
AUDIN 10K
RGA(8:1) VCC
3900pF
R331
8 22 1 2
2

RGA8
7 23 RGA7 R319 1.5K
6 24 RGA6 1K
5 25

2
RGA5 C332
1

4
3
26
27
RGA4
RGA3
_DKRD 40 _DKRD iRIGHT U15 6800pF
RIGHT
2 28 RGA2 _DKWD 41 _DKWD -LF347

1
1 29 RGA1
DKWE 42
9 R332
2 R333 5 U15 CN3
DKWE /TL084 8
1
10K
2
10K
1
+ R334
E3311
6800pF

10 +

+
-
LF347 7 1 2 2 2 SIGNAL

/TL084 1 2 1K 0 2 1
6 C334 22uF-NP 3
-

2
SHIELD

1
AVref RCA JACK
R335 1

2
C333 SHORTBAR

G
12 DMAL Q331 MPF102 2K

3
DMAL
R336

2
RIGHT
1 2
3900pF

1
31 CCK
CCK 470K
32 CCKQ AUDIO
CCKQ AUDIO

RIGHT 33
11 LEFT 34
_RST _RESET

1
R337
10K

2
C321
1 2 MONO
3900pF

1
R321 R345

1
1 2 R327 22K
1.5K 10K

2
AUDOUT

2
2
C322
iLEFT U15 6800pF
AUDIO LEFT
-LF347

1
13 R322
2 R323 3 U15 CN4
+AV
/TL084 14
1
10K
2
10K
1
+ R324
E3211 6800pF
+

+
-
+AV LF347 1 1 2 2 2 SIGNAL

12 /TL084 1 2 1K 0
1

2 1
R347 2 C324 22uF-NP 3
-

2
SHIELD

2.7K

S
1488

1
2 RCA JACK
R346 AVref R325 1

2
C323
2

SHORTBAR

G
2 3 MPF102 2K

3
1 2 2N3906 Q321
_LED 10K 1 R349
LEFT
R326

2
1 2 1 2
3900pF

1
U28 Q341 3 33K
0.01uF
470K
AUDIO
1

4.7K AUDIO

R348 C349
Note: LED off, Filters bypassed
2

-AV
AUDIO
AUDIO FILTERS
PAULA PREFERS THE TRADITIONAL MODES
DESIGN BY: DATE
c 1991 Commodore Business Machines G. Robbins 03/13/92 Commodore
Information contained herein is the unpublished, DRAW: GRR 03/13/92
confidential and trade secret property of LAST: GRR 09/09/92 Schematic A1200 R1d
Rev.1.38 (06.09.2012)

Commodore Business Machines, Inc. Any use, CHKD: C/A1200 Main Board

A1200 Rev 1->1d PCB

reproduction or disclosure of this information APPR:
without the prior written permission of USED ON NEXT ASSY
"Channel Z"
Commodore is strictly prohibited. SIZE REV

C.A.D. Generated
C/A1200 364718
C 364717 1a
SCALE SHEET 5 OF 13
No manual changes may be made to this document
PATH: /project/a300/channel_z.rev1 sheet5
© rebuild for www.amigawiki.org · for private use only
 GENERAL DECOUPLING
VCC

15 NC

IVcc1 128
70
71

90

44
57

10
16
17
27
43
52
53
61

Vcc2 25
Vcc3 65
Vcc4 89
7
8

Vcc1 1
20
62
Vcc1

Vcc2

Vcc3

Vcc4

Vcc5

Vcc6

Vcc7

VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7

NC

15
52
55
U0

Vcc1
Vcc2
52

Vcc1

Vcc2

Vbb
C1A C1B
U1 C1C C1D C0A C0B C0C C0D C5A C5B C20A C20B
U20
C20C C20D
NC

POWER
_BGACK
53 NC C2X
POWER U5

2
C2A nc1 C2B
0.047uF
79 NC 0.047uF 0.047uF 0.047uF 0.22uF 0.22uF 0.22uF 0.047uF POWER 0.22uF 0.047uF U2 24 NC
0.22uF 0.22uF 0.22uF 0.22uF

33 IVss1
nc2 nc2

Gnd1
Gnd2
Gnd3
Gnd4

Vss1
Vss2
Vss3
Vss4
Vss5
Vss6
Vss7
Vss8
2

1
0.22uF 0.33uF 0.22uF

GND10
GND11
GND0
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9

1
GND10

GND11

GND12

GND13
GND1

GND2

GND3

GND4

GND5

GND6

GND7

GND8

GND9

Gnd1

Gnd2

Gnd3
3
24
45
66
4
3
20
21
68
69
72
89
100
26
43
58
59

5
6
7
8
9
12
14
19
30
41
51
63

119
10
32
45
54
77
96
107

82
42
58
AUDIO DECOUPLING
VIDEO DECOUPLING +12V

2
R301
+VID 10
VCC +AV

1
VCC +VID
FB401A
FB992

1
FB 2
FB 1

C301 C303
+

1
FB401B
30
56
83

22
23
43
44

12

19
1
FB 2
Vcc1 Vcc2
-
2

VDD0

VDD1

VDD2

Vaa1
Vaa2
Vaa3
Vaa4
0.22uF

16

16
20
C408 C407 C409 22uF

2
+ + + U12
1

Vcc1

Vcc1

Vcc1

V+
0.22uF U4 0.22uF 0.22uF C23 C34 FB402D
1
FB 2
0.047uF 0.047uF U30 0.47uF 0.47uF 0.047uF 0.22uF
U15
4

U32 U23 U34 POWER

POWER POWER
Vcc1

C199 C4A C4B C32 0.047uF 0.047uF - FB402C - C30B C30A C30C C30D - C12B C12A
Gnd1

8 Gnd1

8 Gnd1
X1

V-
1
FB 2
2

2
100uF
VSS0

VSS1

VSS2

GND1
GND2
GND3
GND4
GND5
1000uF 10uF C302 C304
+
10

11

1
FB402B
Gnd2

Gnd1

0.22uF 1 AUDIO
FB 2 Gnd1 Gnd2
2
1
2

1
33
53

1
2
20
21
28

24
FB402A
1
FB 2
0.22uF - 22uF

2
GROUND VIDEO

2
R302 -AV
VIDEO
10
Note: As of Rev 1C, logic and video gound and power are

1
the same net, but reouted discretely except at DAC! -12V

Also added C30C and C30D for overkill DAC decoupling.

AUDIO POWER
VCC

2
R309
1
VCC

1
VIDEO OUT
1

2
R250 R251 R252 R253 R303
CN9

30
4.7K 4.7K 4.7K 4.7K 1.02K
AVref

Vcc
2

1
VCC C307 C3
+

2
U3 37
E251 +12V A_Gnd

_VSYNC 1
68 2
2
1100pF VSYNC 12
12 2 1 E263 - POWER
E301

1
E252 FB
23 0.01uF1 470uF 0.22uF C306

GND
23 +5 200 C305
_HSYNC +

FB 1

1
1 2 2
68 1100pF HSYNC 11
11 1 E264 R304

8
2 2
E253 FB
22
22 +12 0.01uF1 200 1.02K
_CSYNC_B 1
47 2
2
1100pF CSYNC 10
10 2
2
1 E265 0.22uF - 10uF

2
E254 FB
21
21 -5v 0.01uF1 200
DR 1
47 2
2
1100pF DR 9
9
2

E255 20
20 GND
DG 1
47 2
2
1100pF DG 8
8
-12V
E256 19
19 GND
DB 1
47 2
2
1100pF DB 7
7 AUDIO
E257
DI 1 2
1100pF
18
18
Note: Ground interconnection near audio jacks.
68 2 DI 6
6
E258 17
17
AB 1
200
FB
2
2
1 47pF B 5
5
E259 16
16
AG 1
200
FB
2
1 47pF 4 E266
E260
2 G 4
15
15 _CCK 100pF1
2 1
CCK_B
AR 1
200
FB
2
1 47pF 3
2 68
E267
E261
2 R 3
14
14 100pF1
2 1
PIXELSW
_XCLKEN 2
100pF1 2
1
68 _XCLKEN 2
2
PIXLSW 2 68
E262 13
13
XCLK 2
*1 2
1
68 XCLK 1
1
DGND

DB23S
VIDEO VIDEO

PARTY OUT OF BOUNDS, WHAT A MESS...

DESIGN BY: DATE
c 1991 Commodore Business Machines G. Robbins 03/13/92 Commodore
Information contained herein is the unpublished, DRAW: GRR 03/13/92
confidential and trade secret property of LAST: GRR 10/10/92 Schematic A1200 R1d
Rev.1.38 (06.09.2012)

Commodore Business Machines, Inc. Any use, CHKD: C/A1200 Main Board

A1200 Rev 1->1d PCB

reproduction or disclosure of this information APPR:
without the prior written permission of USED ON NEXT ASSY
"Channel Z"
Commodore is strictly prohibited. SIZE REV

C.A.D. Generated
C/A1200 364718
C 364717 1a
SCALE SHEET 6 OF 13
No manual changes may be made to this document
PATH: /project/a300/channel_z.rev1 sheet6
© rebuild for www.amigawiki.org · for private use only
 VCC

1
10K 10K

R511B R511A

2
D(31:0)
U7 S
43 _KB_DATA VCC
C
44 _KB_CLOCK
29 D7
23 30

1
D6
22 31 10K 10K 10K
CN7
D5
21 32 D4
20 33 11 R511D DB25S
_FIRE1 R511F R511C

2
D3 PA7
19 34 VCC
A(23:0) 18 35
D2
10 E511 _STROBE
17 36
D1 PA6 _FIRE0 1
68 2
2
1100pF
1
14 _AUTO 1 2 E524
D0
16 PA5
9 _RDY 0 E512 1 2 D0 2 47 2 10.01uF

8520 68 2 1100pF 15 _ERR

NC
PA4
8 _TRK0 1 E513 1 2 D1 3
1100pF 16 _INIT E525
7 2 E514
68 2
D2 100pF1
2 1
_RESET
_WPROT 4 68

VIA
1 2 2
PA3
38 RS3 68 2 1100pF 17 SELI
11 39 RS2 PA2
4 _CHNG 3 E515 1 2 D3 5
10 41 RS1 68 2 1100pF 18
9 42 RS0 PA1
3 _LED 4 E516 1 2 D4 6
8 68 2 1100pF 19
PA0
2 NC 5 E517 1 2 D5 7
68 2 1100pF 20
6 E518 1 2 D6 8
68 2 1100pF 21
7 E519 1 2 D7 9
PB7
19 7 68 2 1100pF 22
25 E520 _ACK 10
_ODD_CIA _CS
18 6 100pF1
2
2 68
1
23
PB6 E521 2 1 BUSY 11
PB5
17 5 100pF1 2 68 24
E522 2 1 POUT 12
PB4
16 4 100pF1 2 68 25
24 E523 2 1 SEL 13
_W
PB3
15 3 100pF1 2 68

27 E PB2
14 2

PB1
13 1
23
_INT2 _INT
PB0
12 0
PARALLEL PORT
PPD(7:0)
21
_VSYNC TICK

37 _RESET _PC
20

_F
26

3
D573 D572 Q571 R571

1
1 2 1
2N3904
1N4001 1N4001 2.7K

2
VCC 2 1N914

3
10K
R572
D571

1
U8 S
43
VCC
C
44
VCC
29

1
D7
31 30 10K
13 1488 U28
OPTIONAL
D6
30 31 D5
29 32 R511E 11

2
D4 12
28 33 D3 PA7
11
27 34 D2
26 35 10

RS232
D1 PA6
25 36 D0
24 9
PA5
U28 DB25P
8520 PA4
8
_xTxD
10
8 NC
FG 1
7
_TxD 9 14 sTxD
NC
CN6
VIA
PA3 NC
38 E551 TxD 2
U29
1 2
RS3 2
11 39 RS2 PA2
4 1489 1488 68 2 1100pF 15 TxC
NC
10 41 3 1 E552 RxD 3
9 42
RS1
3 _RxD 100pF1
2
2 68
1
16 sRxD
NC
RS0 PA1
8
2 _xRxD 5
1488 U28 E553 1
68 2
2
1470pF
RTS 4
17 RxC
NC
PA0 E554 CTS
6 2 1 5
4 470pF1 18 AI 0.22uF
E555 2
2 68
1 DSR 6 1 2
AUDIN
470pF1 2 68 19 sRTS
NC
C551
NC
25
PB7
19 _MTR U29 12 1489
+12V
SG 7
20 DTR E557
_EVEN_CIA _CS
18 11 13 E556 CD
1 2
10.01uF
PB6 _SEL3 470pF1
2
2 68
1 8
21 SQD
47 2

NC
PB5
17 _SEL2 U29 NC
5 1489
E561
0.01uF1
2
2 47
1 +V 9
22 RI 2 1 E558
16 6 4 E562 -V 100pF1
24
PB4 _SEL1 0.01uF1
2
47
1 10
23 SS
2 68
R_W _W NC
2 NC 0.22uF
PB3
15 _SEL0 U29 9 1489
AO 11
24 CLK
NC
1 2
AUDOUT
27 14 8 10 -12V sCD C552
E E PB2 _SIDE NC 12
25 BZ
NC
13 sCTS
23
PB1 DIR NC 13

_INT6 _INT
12
PB0 _STEP
VCC
21
_HSYNC TICK
1

1K

37 20 NC R512
_RST
2

_RESET _PC

_F
26 _INDEX
D574
1

1N4001
2

VCC

SERIAL AND PARALLEL PORTS

DESIGN BY: DATE
c 1991 Commodore Business Machines G. Robbins 03/13/92 Commodore
Information contained herein is the unpublished, DRAW: GRR 03/13/92
confidential and trade secret property of LAST: GRR 09/09/92 Schematic A1200 R1d
Rev.1.38 (06.09.2012)

Commodore Business Machines, Inc. Any use, CHKD: C/A1200 Main Board

A1200 Rev 1->1d PCB

reproduction or disclosure of this information APPR:
without the prior written permission of USED ON NEXT ASSY
"Channel Z"
Commodore is strictly prohibited. SIZE REV

C.A.D. Generated
C/A1200 364718
C 364717 1a
SCALE SHEET 7 OF 13
No manual changes may be made to this document
PATH: /project/a300/channel_z.rev1 sheet7
© rebuild for www.amigawiki.org · for private use only
 INTERNAL FLOPPY
FLOPPY LOGIC
E586
_CHNG 1

68 2
2
1 100pF
2 1

4 3 NC

NC 6 5
E596
_INDEX 1

68 2
2
1 100pF
8 7
FLOPPY FUNCTIONS E580
_SEL0 1 2
10 9

U5
27 2 1 100pF
71 67 E595
_MTR _MTR _MTRON _MTR0 _SEL1 1 2
100pF
12 11
27 2 1
72
_SEL0 _SEL NC 14 13
E599
_MTR0 1 2

AA_GAYLE
16 15
27 2 1 100pF
E593
DIR 1 2
18 17

4145f023a 27 2 1 100pF
E592
_STEP 1

27 2
2
1 100pF
20 19
E591
_DKWDB 1

27 2
2
1 100pF
22 21
E590
_DKWEB 1

27 2
2
1 100pF
24 23
E589
_TRK0 1

68 2
2
1 100pF
26 25
E588
_WPROT 1

68 2
2
1 100pF
28 27
E582
_DKRD 1

68 2
2
1 100pF
30 29
E587
_SIDE
U26
1 2
74LS86 32 31
1 27 2 1 100pF
3 _MTRX E581
2 _RDY 1

68 2
2
1 100pF
34 33

74LS86
1
3 E594
2 _SEL3 1

27 2
2
1 100pF
U26X _MTRX
E583 1 2

CN11
74LS86 27 2 1 100pF
_DKWD 4
6
U26 _SEL2
E584 1 2

_DKWDB 27 2 1 100pF

CN5
5 E585
_RESET 1

27 2
2
1 100pF
74LS86
4
6
5 DB23S
U26X _RDY 1
13 SIDE
_RD 2
14 _WPROT
VCC 3
15
U26
_TRK0
13 74LS86 4
11 _DKWEB 16 _WE
12 5
DKWE 17 _WD
74LS86
13 6
11 18 _STEP
12 7

U26X _MTRX 8
19 _DIR

20 _SEL3
_SEL2 9
21 _SEL1
_RESET 10
See OOPS on Page 2... 11
22 _INDEX
_CHNG
U26 and U26X may overlap! 12
23

VCC

E598 1 2
FB
2 1
200 0.01uF

EXTERNAL FLOPPY
+12V
E597 1 2
FB
200 2 1
0.01uF

FLOPPY POWER
VCC
4-PIN SIL
1
2
+12V 3

CN12
4
2

C591 C592
Note: Some drives are +5 only...
0.01uF 0.01uF
1

DECOUPLING +12V

D575
-12V

1N4001
1

2
VCC
1N4001 D576
2

1
14
22

22

14

14

1
Vcc1

Vcc1

Vcc1

Vcc1

Vcc1

Vcc2

C7 C8 C26 C29 C28A C28B

U7 U8 U26 U29 U28
0.22uF 0.22uF 0.047uF 0.047uF 0.047uF 0.047uF
Gnd1
Gnd1

Gnd1

Gnd1

Gnd1
1

1
1

THE REST OF THE FLOPPY STUFF

DESIGN BY: DATE
c 1991 Commodore Business Machines G. Robbins 03/13/92 Commodore
Information contained herein is the unpublished, DRAW: GRR 03/13/92
confidential and trade secret property of LAST: GRR 09/09/92 Schematic A1200 R1d
Rev.1.38 (06.09.2012)

Commodore Business Machines, Inc. Any use, CHKD: C/A1200 Main Board

A1200 Rev 1->1d PCB

reproduction or disclosure of this information APPR:
without the prior written permission of USED ON NEXT ASSY
"Channel Z"
Commodore is strictly prohibited. SIZE REV

C.A.D. Generated
C/A1200 364718
C 364717 1a
SCALE SHEET 8 OF 13
No manual changes may be made to this document
PATH: /project/a300/channel_z.rev1 sheet8
© rebuild for www.amigawiki.org · for private use only
 VCC

KB LEDS
KEYBOARD TAIL VCC

1
R631

CN13
10K Q631
2 5-PIN SIL

2
R632
1 2 1
_IDE_LED 1
4.7K
VCC 2
3
MEMBRANE-31 2N3906 3
VCC 4

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

1
VCC 5

1
R637
* Q634
2

2
R638
1 2
_CC_ENA 1

CN14
*
3
*
OPTIONAL

KEYBOARD MPU
VCC

VCC

1
VCC R633
R621 10K Q632
2

2
4.7Kx9

1
R634
1 2
_MTR0 1
4.7K
3

2
4
3
5
6
9
7
2N3906

VCC
VCC

PD7 39

1
R635

U13
10K Q633
22pF Y621 2

2
42 OSC2 PD5 37

1
R636
2 1 1 2 R639
_LED
C621 PD4 36 4.7K 1 100
2

2
R628
3MHz PD3 35 3
1M 2N3906
PD2 34
1

22pF
43 OSC1 PD1 33
2 1

C622 PD0 32
R622
PC7 24 1 2
100
PC6 25
NC 3 NC1 PC5 26
NC 18 NC2
NC 23 NC3 PC4 27
NC 40 NC4
PC3 28 VCC
R624
PC2 29
4.7Kx9

1
PC1 30

68HC05C PC0 31

2
4
3
5
6
9
PB7 21
PB6 20
KEYBOARD PB5 19
PB4 17
MICRO PB3 16
PB2 15
PB1 14 _KB_CLOCK
PB0 13 _KB_DATA
7-PIN SIL

PA7 5
CN17
1

1
R625
PA6 6 2
*
PA5 7 3

2
PA4 8 4 KB TEST
PA3 9 NC 5 VCC
VCC NEW ON REV 1E PCB
VCC PA2 10 6

PA1 11 7

1
2 R626
_IRQ
PA0 12 *

2
TCMP 38 _KB_RESET
VCC
1 _RESET TCAP 41

1
R623
VCC 10K

44
4
2

Vdd

Vpp
VCC C13
1

1
R629 U13
10K POWER
2 0.22uF
+
2

2
Vss
1 _PWR_BAD

22
RH5VA43A NC

3
- C629
1

U49 0.33uF
POWER OK
2

THE NEW HOME OF THE KEYBOARD VIRUS

DESIGN BY: DATE
c 1991 Commodore Business Machines G. Robbins 03/13/92 Commodore
Information contained herein is the unpublished, DRAW: GRR 03/13/92
confidential and trade secret property of LAST: GRR 09/09/92 Schematic A1200 R1d
Rev.1.38 (06.09.2012)

Commodore Business Machines, Inc. Any use, CHKD: C/A1200 Main Board

A1200 Rev 1->1d PCB

reproduction or disclosure of this information APPR:
without the prior written permission of USED ON NEXT ASSY
"Channel Z"
Commodore is strictly prohibited. SIZE REV

C.A.D. Generated
C/A1200 364718
C 364717 1a
SCALE SHEET 9 OF 13
No manual changes may be made to this document
PATH: /project/a300/channel_z.rev1 sheet9
© rebuild for www.amigawiki.org · for private use only
 16-BIT ROM 32-BIT ROM FLASH MEMORY
A(23:0) A(23:0) A(23:0)

R598
1 1 2

20 42 A19* 21 * 42 A19* 21 42 A19*

1 1 1 30 30
U6B
19 20 20 18 18
U6A
R599
18 2
A18*
U6 30 19 1 2 2
A18*
30 19 2
A18*
30 17 2
A17
17 2
A17

U10
A17 D15 A17 D15 A17 D15 A16 A16
17
16
15
33
34
35
A16
A15
A14
D14
D13
D12
28
26
24
31
30
29
18
17
16
27
33
34
35
A16
A15
A14
D14
D13
D12
28
26
24
31
30
29
18
17
16
33
34
35
A16
A15
A14
D14
D13
D12
28
26
24
15
14
13
16
15
14
3
29
28
A15
A14
A13 OPT
16
15
14
3
29
28
A15
A14
A13
U11
14 36 21 28 15 36 21 28 15 36 21 12 13 4 13 4 OPT
13 37
A13 D11
19 27 14 37
A13 D11
19 27 14 37
A13 D11
19 11 12 25
A12 N 21 12 25
A12
N 21
A12 D10 A12 D10 A12 D10 A11 D7 A11 D7
12 38 A11 D9
17 26 13 38 A11 D9
17 26 13 38 A11 D9
17 10 11 23 A10 D6
20 31 11 23 A10 D6
20 23
11 39 A10 D8
15 25 12 39 A10 D8
15 25 12 39 A10 D8
15 9 10 26 A9 D5
19 30 10 26 A9 D5
19 22
10 40 A9 62408 D7
29 24 11 40 A9 62408 D7
29 24 11 40 A9 62408 D7
29 8 9 27 A8 28F20 D4
18 29 9 27 A8 28F20 D4
18 21
9 41 A8 D6
27 23 10 41 A8 D6
27 23 10 41 A8 D6
27 7 8 5 A7 2 MBit FLASH D3
17 28 8 5 A7 2 MBit FLASH D3
17 20
8 3 Mbyte ROM 25 9 3 Mbyte ROM 25 9 3 Mbyte ROM 25 7 6 15 7 6 15
A7 D5 22 A7 D5 22 A7 D5 6 A6 D2 27 A6 D2 19
7 4 A6 D4
23 21 8 4 A6 D4
23 21 8 4 A6 D4
23 5 6 7 A5 D1
14 26 6 7 A5 D1
14 18
6 5 A5 D3
20 20 7 5 A5 D3
20 20 7 5 A5 D3
20 4 5 8 A4 D0
13 25 5 8 A4 D0
13 17
5 6 A4 D2
18 19 6 6 A4 D2
18 19 6 6 A4 D2
18 3 4 9 A3 24 4 9 A3 16
4 7 A3 D1
16 18 5 7 A3 D1
16 18 5 7 A3 D1
16 2 3 10 A2 3 10 A2
3 8 A2 D0
14 17 4 8 A2 D0
14 17 4 8 A2 D0
14 1 2 11 A1 2 11 A1
2 9 A1 16 3 9 A1 16 3 9 A1 0 1 12 A0 1 12 A0
1 10 A0
VCC 2 10 A0
VCC 2 10 A0
VCC

32 32 32 31 31
_BYTE _BYTE _BYTE _WE _WE _WE

13 13 13 24 24
_OE _OE _OE _OE _OE _OE _OE _OE

11 11 11 22 22
_ROMEN _CS _ROMEN _CS _CS _CE _CE

R593
1 2
_WIDE
470
D(31:0) D(31:0) D(31:0)
74F139
4
2 A0 OPT _0 5
_UDS _1 NC
3 A1 N _2
_3
6
7
NC
NC U37

1 _EN
VCC
VCC

74F139
12
14 A0 OPT _0

22

22
11 NC
_LDS _1
U37
22

13 A1 N _2 10 NC

Vcc1

Vcc1
C6A C6B 9 NC
Vcc1

1
_3

_EN
C6 U6A U6B A(18)
1

U6 0.22uF 0.22uF VCC

15
2

2
Gnd1

Gnd2

Gnd1

Gnd2
0.22uF Vpp
2
Gnd1

Gnd2

_FLASH

12
31

12
31
12
31

32

32
1

1
16
DECOUPLING DECOUPLING

Vcc

Vpp

Vcc

Vpp
C37 C10A OPT C10B C11A OPT C11B

Vcc1

1
U37 N N
OPT U10 U11
N OPT OPT OPT OPT OPT

Gnd1
if rom16="yes" if rom32="yes" 0.047uF 0.22uF N 0.22uF

2
N N 0.22uF 0.22uF N N

Vss

Vss
8

16

16
16 AND 32-BIT SOCKETS MAY OVERLAP! DECOUPLING
if flash="yes"

REAL TIME CLOCK

R919 VCC
OPTIONAL FLASH MEMORY
10K
1

VCC
A(23:0)
8
7
9
6
5
4
3
2

R912
D(31:0) 5
4
8
6
A3
A2
10K
TP9
1

3 5 A1 16

PROGRAMMING VOLTAGE
_ALARM
2 4 A0 1
ADJ
3
U9
2

19 15 D3 R917 +12V +12V

18 14 D2 1K +12V
17 13 D1 470 D911 1N914
1

16 12 D0 1 3

1
2 1 R653 VCC
Q652
R911 10K 2
VCC VCC VCC VCC RF5C01A D912 VCC
1

1
R659

2
1 2 R658
1 * Vpp
2

470
R918 R914 R915 R916 1N914 3
3

2
47K 10K 10K 6.8-45pF TC9 470 Q651 3
R651
10K 18
BT9 PE12 1 2 1 2N3906
1

OSCIN
2 1 2 1 2N3904

1
4.7K
20

2 R913 R654
_PWR_BAD Y9

1
CS 1 2 R652
C913 7 NC 2 1K
2

Vcc1

nc1
1 3/V32RT 17 NC C9 10K
_RTC_CS +
1

U9

2
_CS 32768Hz nc2
Ni-Cd

2
Gnd1

3.6V
10UF -
31

30mAH 0.1uF
10

C911
2

9 19
_IORD _RD OSCOUT
2 1 3
11 22pF +12V
_IOWR _WR
VCC

1
REAL TIME POWER R657
10K
R660
Q654
2

2
1 2
1
470
3
Q653 3
R655
1 2 1 2N3906
PE5 2N3904
4.7K

1
if rtc="yes" R656 2
10K

2
OPTIONAL REAL-TIME CLOCK/CALENDAR
ROM - PLAIN AND FANCY - DODADS TOO!
DESIGN BY: DATE
c 1991 Commodore Business Machines G. Robbins 03/13/92 Commodore
Information contained herein is the unpublished, DRAW: GRR 03/13/92
confidential and trade secret property of LAST: GRR 09/09/92 Schematic A1200 R1d
Rev.1.38 (06.09.2012)

Commodore Business Machines, Inc. Any use, CHKD: C/A1200 Main Board

A1200 Rev 1->1d PCB

reproduction or disclosure of this information APPR:
without the prior written permission of USED ON NEXT ASSY
"Channel Z"
Commodore is strictly prohibited. SIZE REV

C.A.D. Generated
C/A1200 364718
C 364717 1a
SCALE SHEET 10 OF 13
No manual changes may be made to this document
PATH: /project/a300/channel_z.rev1 sheet10
© rebuild for www.amigawiki.org · for private use only
 MEMORY CARD CN15
GND 35 1 GND

3 CD1- 36 2 D3

4 D11 37 3 D4
_CC_CD(1)
11
5 D12 38 4 D5 VCC VCC
12
6 D13 39 5 D6

2
13 R717 R718
7 D14 40 6 D7 10K 10K
14

1
D15 41 7 CE1-
_CC_CEU
A(23:1) 15
10 CE2- 42 8 A10

43 9 _CC_CEL
R714A 25
RFSH OE-
_CC_OE
NC
1 2 120 11 IORD- 44 10 A11
R714B 24
1 2 120 9 IOWR- 45 11 A9
_CC_IORD
8 46 12 _CC_IOWR
U45 74LS245 17
A17 A8

18 2 0 13 A18 47 13 A13
CC_A0 17
B1 A1
3 23 18
B2 A2
16 B3 A3 4 22 14 A19 48 14 A14 VCC
23 15 A4 5 21 19
20 B4
14 6 20 49 15
19 13
B5 A5
7 19 20
A20 WE-/PGM-
_CC_WE_PGM
B6 A6
18 12 8 18 50 16
B7 A7 A21 BUSY-/IREQ-
_CC_BUSY_IREQ

_G_EN
17 11 A8 9 17 21
B8

DIR
Vcc 51 17 Vcc Vpp

52 18

19
Vpp2 Vpp1

1
16 A22 53 19 A16

Warning: U46 22
74LS245 15 A23 54 20 A15 C701 C702

1
16 18 A1 2 16 23
15 B1
17 3 15 12 A24 55 21 A12
Byte Swapped 14 16
B2
B3
A2
A3 4 14 24 0.22uF 0.22uF

2
13 15 A4 5 13 7 A25 56 22 A7
12 B4
14 B5 A5 6 12 25
11 13 7 11 6 RFU 57 23 A6
BUS PART 72 7 10 12
B6 A6
A7 8 10
XD(15) B7 NC

_G_EN
73 6 9 11 A8 9 9 5 RFU 58 24 A5
XD(14) B8
U20 5

DIR
XD(13) 74 CC_RESET
XD(12) 75 4 4 WAIT- 59 25 A4
76 3

19
XD(11) _CC_WAIT

1
XD(10) 78 2 3 IOACK- 60 26 A3
XD(9) 79 1 NC
XD(8) 80 0 U47 74LS245
2 REG 61 27 A2
BUDGIE 81 15 8 18 2 8 1 BVD2/DA 62 28 A1
_CC_REG
XD(7) B1 A1
391425 82 14 7 17 3 7
XD(6)
83 13 6 16
B2 A2
4 6 0 BVD1 63 29 A0
_CC_BVD(2)
XD(5) B3 A3
84 12 5 15 5 5
XD(4)
85 11 4 14
B4 A4
6 4 0 D8 64 30 D0
_CC_BVD(1)
XD(3) B5 A5
86 10 3 13 A6 7 3 8
XD(2)
2 B6
XD(1) 87 9 12 B7 A7 8 2 1 D9 65 31 D1

_G_EN
88 8 1 11 A8 9 1 9
XD(0) B8

DIR
2 D10 66 32 D2
VCC 10
67 33

19
CD2 WP/IOCS16-
_CC_WP
BGACK_

1
_CC_CD(2)
XEN_

GND 68 34 GND
2

R701 CC_A(25:0)
10K
99

100

CC_D(15:0)
1

VCC
2

R716
10K
74LS245 VCC R715
1

10K

1
18 2
_OE B0 A0 _CC_OE
17 3
_WE B1 A1 _CC_WE_PGM

2
4
3
5
6
9
7
8
16 4
_IORD B2 A2 _CC_IORD
15 5
_IOWR B3 A3 _CC_IOWR
14 6 75
_UDS B4 A4 _CC_CEU _CC_CD(1) _CC_CD(1) CARD FUNCTIONS
13 7 76
_LDS B5 A5 _CC_CEL _CC_CD(2) _CC_CD(2)

U5
12 8 77
_REG B6 A6 _CC_REG _CC_BVD(1) _CC_BVD(1)
2
11 9 78
PE5 PE5
_CC_WAIT B7 A7 _WAIT _CC_BVD(2) _CC_BVD(2)
_OE

DIR

PE12
1 PE12
79 _CC_WP
_CC_WP 4 0.22uF
19

NOISE NOISE
1

U43 _CC_BUSY_IREQ 80 _CC_BUSY 1 2

C711

7
_CC_ENA
_REG
81
_REG

_WAIT
4145f023a
_WAIT
_IORD 19 _IORD
AA_GAYLE
_IDE_IRQ
12 _IDE_IRQ
18
_IOWR _IOWR
13
9
_IDE_CS(1) _IDE_CS(1)
_OE _OE
14
8 _WE
_ID_CS(2) _IDE_CS(2)
_WE
6 84 _INT2
_CC_ENA _CC_ENA _INT2

_INT6
83 _INT6
27
CC_A0 CC_A0

5
CC_RESET CC_RESET

2
R715Y R715X
10K 4.7K

1
VCC
20

20

20

20
Vcc1

Vcc1

Vcc1

Vcc1

C43 C45 C46 C47

U43 U45 U46 U47
0.22uF 0.22uF 0.22uF 0.22uF
10 Gnd1

10 Gnd1

10 Gnd1

10 Gnd1
1

THE KISSY FACE CREDIT CARD MONSTER

DESIGN BY: DATE
c 1991 Commodore Business Machines G. Robbins 03/13/92 Commodore
Information contained herein is the unpublished, DRAW: GRR 03/13/92
confidential and trade secret property of LAST: GRR 09/09/92 Schematic A1200 R1d
Rev.1.38 (06.09.2012)

Commodore Business Machines, Inc. Any use, CHKD: C/A1200 Main Board

A1200 Rev 1->1d PCB

reproduction or disclosure of this information APPR:
without the prior written permission of USED ON NEXT ASSY
"Channel Z"
Commodore is strictly prohibited. SIZE REV

C.A.D. Generated
C/A1200 364718
C 364717 1a
SCALE SHEET 11 OF 13
No manual changes may be made to this document
PATH: /project/a300/channel_z.rev1 sheet11
© rebuild for www.amigawiki.org · for private use only
 MEMORY EXPANSION IDE DRIVE

DRD(31:0)

BDRA(8:0)

A(23:0)

D(31:0) DIL_44
CN16
P9A
DIL_40
VCC P9B
DIL_40
VCC
_RESET
D(31:0)
1 2

31 3 4
1 2 1 2
16

16
3 4
0
3 4 Warning: 30
17
5 6

31 15 29 7 8

17
5 6
1
5 6
Byte Swapped 18
30 14 28 9 10
7 8 7 8
18 2 19
29 13 27 11 12
9 10 9 10
19 3 20
28 12 26 13 14
11 12 11 12
20 4 21
27 11 25 15 16
13 14 13 14
21 5 22
26 10 24 17 18
15 16 15 16
22 6 23
NC
25 9 19 20
17 18 17 18
23 7
NC
24 8 21 22
19 20 19 20

_IOWR 23 24
_BWE 21 22 _ROE _INT6 21 22 _SPARE_CS
_IORD 25 26
_BRAS(0) 23 24 _BRAS(1) _RTC_CS 23 24 _PWR_BAD
_WAIT 27 28
NC

_BCAS_UU 25 26 _BCAS_UM _IORD 25 26 _IOWR

NC
29 30
_BCAS_LL 27 28 _BCAS_LM 5
27 28

4
_IDE_IRQ 31 32
NC

29 30 CCK_A 3
29 30 A(23:0)
0
NC
2 3 33 34
31 32 31 32
1 23
8 22 2 35 36
33 34 33 34
2 21 4
7 20
_IDE_CS(1) 37 38

3
35 36
19
35 36 _IDE_CS(2)
6 18
_IDE_LED 39 40 VCC
VCC
37 38 37 38
4 +12V 17

2
16 R971
5 41 42
4.7K
39 40 39 40 _RESET

1
43 44
Note: Only this bit of P9A/B
loaded for 2M-byte PCB!

MEMORY EXPANSION AND THE IDE DRIVE

DESIGN BY: DATE
c 1991 Commodore Business Machines G. Robbins 03/13/92 Commodore
Information contained herein is the unpublished, DRAW: GRR 03/13/92
confidential and trade secret property of LAST: GRR 09/09/92 Schematic A1200 R1d
Rev.1.38 (06.09.2012)

Commodore Business Machines, Inc. Any use, CHKD: C/A1200 Main Board

A1200 Rev 1->1d PCB

reproduction or disclosure of this information APPR:
without the prior written permission of USED ON NEXT ASSY
"Channel Z"
Commodore is strictly prohibited. SIZE REV

C.A.D. Generated
C/A1200 364718
C 364717 1a
SCALE SHEET 12 OF 13
No manual changes may be made to this document
PATH: /project/a300/channel_z.rev1 sheet12
© rebuild for www.amigawiki.org · for private use only
 VCC
A(31:0)

P1 HOLES &c.
D(31:0) 31 2
30 1
29
28
27
26
3

5
4

6
POWER INPUT
25 8
24 7 LF1A
LF1 LINE FILTER

CN8
10 1
FB 2 10 11 CN1 MT1
9
23 12 10 11 CN2 MT2
22 11 4 5
21 14 24 25 CN5 MT3
20 13 LF1B C802 C821 +

1
19 +12V 26 27
18 15
16 1
FB 2 CN6 MT4

EXPANSION
17 0.01uF - 26 27 CN7
18
MT5

2
16 17 1 8 47uF
20 7 24 25 CN9 MT6
19 6 LF1C C803 C822 +

1
15 22 1
FB 2 69 70 CN15 MT7
14 21 3 SH 4

CONNECTOR
0.01uF - -12V
13 24 +12 GND MT8

2
12 23 3 6 47uF
-12V
11 26 5
10 25
SH +5 C800 LF1D

2
9 28 2 1 1
FB 2
8 27 VCC
0.01uF
30
V1 V9

1
29 2 7
7 32
V2 V10
6 31 C801 C804 C811 +

1
5
33
34 5-PIn SQ V3 V11
4
3 0.01uF 0.22uF -
36
V4 V12

2
2 35 1000uF
1 38
V5 V13
0 37

39
40
V6 V14
31 42
V7 V15
30 41
29 44
V8
NOTE: HEAVY LINES INDICATE A
28 43
27 46
26 45
25
24 47
48 SINGLE POINT CONNECTION
50
49
23 52
22 51
21 54
20 53
19 56
18 55
17 58
16 57

TEST ACCESS TERMINATION

60
59
15 62
14 61
13 64
12 63
11 66
10 65 10-PIN SIL VCC
9 68 1
8 67 CPUCLK
70 2 1 2 R951A
69 _AS _HLT
7 3 4.7K
1 2 R951B
72
6 71 _DS _RST
5 4 4.7K
74
4 73 R_W 1 2 R951C
3 76 5 SIZE_0
2 75 _DSACK_0 4.7K
1 2 R951D
1 6 SIZE_1
_IPL(2:0) 78
_DSACK_1 4.7K
TP1
0 77
80 7 1 2 R951E
79 _ROMEN R_W
FC(2:0) 2 82 8 4.7K
1 2 R951F
1 81 _CDIS _AS
0 9 4.7K R951G
83
84 NC _IPEND _KB_RESET _DS 1 2

10 4.7K
_RST 85
86
_HLT
R952A
_ECS NC
87
88 NC _OCS _DSACK_0 1 2
470 R952B
SIZE_1 89
90
SIZE_0 10-PIN SIL _DSACK_1 1 2

1 470
_AS 91
92
_DS CCK
2 R101
R_W 93
94
_BEER CCKQ _BEER 1 2

3 470 R103
_STERM NC
96
95
_AVEC _RAMEN _AVEC 1 2

4 470
_DSACK_1 97
98
_DSACK_0 _REGEN
5 R102
CPUCLK_A 99
100
E _BLS _CDIS 1 2

6 1K
1 2 R104
102
_OEB _BR
TP2
101
2 7 1K
_CDIS 1 103
104
_RAS
0 8
106
_RMC _CAS
DELETED R1B PCB 105
9 _IPL(2:0)
_CIIN NC
107
108 NC _CIOUT _DWE
10 0 R953A
_CBREQ NC
109
110 NC _CBACK 1 2
470 R953B
_BG 1 1 2
_BR 111
112

RGA(8:1) 2
470 R953C
_BGACK NC
113
114
_BOSS 10-PIN SIL
1 2

1 470
_FPU_CS 115
116
_FPU_SENSE _DBR FC(2:0)
8 2
CCK_A 117
118
_RESET 0 1 2 R953D
120 7 3
119 470 R953E
1 1 2
6 4
_NET_CS 121
122
_SPARE_CS 2
470
1 2 R953F
5 5
_RTC_CS 123
124
_FLASH 470
4 6
_REG 126
_CC_ENA
TP3
125
3 7
_WAIT 127
128
_KB_RESET
2 8 R954A
_IORD 129
130
_IOWR _INT6 1 2
1K
1 9 R954B
_OE 131
132
_WE _INT2 1 2
1K
10
_OVR 133
134
XRDY 1 2 R954C
_OVR 470
_ZORRO 135
136
_WIDE 1 2 R954D
XRDY 470
_INT2 137
138
_INT6
140 1 2 R954E
139 _ZORRO 1K
SYSTEM_1 142 1 2 R592
SYSTEM_0 141 _WIDE 1K
_xRxD 143
144
_xTxD
_CONFIG_OUT 145
146 System Configuration Bits
LEFT 148
RIGHT
147
SYSTEM 1 0 CPU/CPUCLK
149
150 == == ============
+12V -12V 0 0 EC020/14MHz POWER DISTRIBUTION AND DECOUPLING
EDGE_150
GROUND AUDIO 0 1 020/14MHz c 1991 Commodore Business Machines
DESIGN BY:
G. Robbins
DATE
03/13/92 Commodore
Information contained herein is the unpublished,
1 0 030/14MHz
DRAW: GRR 03/13/92
confidential and trade secret property of LAST: GRR 10/10/92 Schematic A1200 R1d
Rev.1.38 (06.09.2012)

Commodore Business Machines, Inc. Any use, CHKD: C/A1200 Main Board

A1200 Rev 1->1d PCB 1 1 030/>14MHz reproduction or disclosure of this information APPR:
without the prior written permission of USED ON NEXT ASSY
"Channel Z"
Commodore is strictly prohibited. SIZE REV

C.A.D. Generated
C/A1200 364718
C 364717 1a
SCALE SHEET 13 OF 13
No manual changes may be made to this document
PATH: /project/a300/channel_z.rev1 sheet13
© rebuild for www.amigawiki.org · for private use only
 REVISIONS
REV DESCRIPTION DATE APRVL MANAGER

1 ADVANCE ENGINEERING RELEASE

4-PIN SIL
1

CN1 2

R3 R2 R1
33 33 33

1 1 1
LED3 LED2 LED1

HDD FLOPPY POWER

2 YELLOW 2 GREEN 2
YELLOW
3 3 3

4 4 4

SHINE ON, SHINE ON

DESIGN BY: DATE
c 1991 Commodore Business Machines B. FENIMORE 7/21/92 Commodore
Information contained herein is the unpublished, DRAW: BAF 7/21/92
confidential and trade secret property of LAST: BAF 7/21/92 SCHEMATIC

A1200 LED PCB ASSEMBLY REV1

Commodore Business Machines, Inc. Any use, CHKD:
reproduction or disclosure of this information APPR: A1200 LED ASSY
without the prior written permission of USED ON NEXT ASSY
Commodore is strictly prohibited. SIZE REV
A1200
364966
Rev.1.38 (06.09.2012)

364963
A 1
C.A.D. Generated SCALE SHEET 1 OF 1
No manual changes may be made to this document
PATH: /user/fenimore/AA600/led_assy sheet1

© rebuild for www.amigawiki.org · for private use only

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