VLSI TECHNOLOGY AND DESIGN ‘Course Code 7620 Credits 4 ‘Scheme of Instruction L T P TOTAL Hours/ Week 3 1 0 40hrs/sem ‘Scheme of Examination a Ww ™ P ° TOTAL = 125 marks 25 25 1100 o o Course Objectives: The course aims to provide the student with: 1. An in depth knowledge of the MOSFET operation and the ability to derive the thresholdvoltage & current equations. 2.An understanding of the theory of CMOS Inverter and Switching characteristics and thecapability to write SPICE programs for various circuits. 3. The capability to design combinational circuits in CMOS logic and draw Layouts for the same. 4. An understanding of the various processes involved in VLSI technology and chip fabricationand design circuits using VHDL. Course Outcomes: After completion of the course the student will be able to: CO1 | Explain the MOSFET operation, Current Voltage Equations, and CMOS Inverter Theory and to solve numerical based on MOSFET and CMOS inverter. C02 | Explain the various MOSFET fabrication processes. CO3 | Write the SPICE programs for modeling MOSFET circuits and to implement complex combinational functions in CMOS logic and draw the layout for the same. C04 | Design simple combinational and sequential circuits using VHDL. PageasUNIT-1 Introduction to VLSI: VLSI Design Flow. MOS transistors: Structures, MOS system under external bias, operation | 10 hrs of MOS transistor (MOSFET), MOS transistors: Threshold voltage MOSFET current-voltage characteristics (CGA), channel length modulation, substrate bias effect. Measurements of parameters ~ Ky, Vro&y. Overview of MOSFET capacitances. UNIT-2 CMOS inverter design: operation, DC characteristics, calculation of VIL, VIH, VTH, VOH and VOL. Noise margins power and area considerations. | 10hrs Latch up and its prevention. Switching Circuit Characteristics: Rise, fall and delay time, gate delays, transistor sizing, static and dynamic power dissipations CMOS logic gate design: Fan in and fan out. Modeling of MOS transistor circuits using SPICE. (Level 1 model equations). UNIT-3 ‘MOS transistor switches: CMOS logic- Inverter, NOR, NAND and combinational logic, Compound gates, Multiplexers, Transmission gates, | 10hrs Latches and Registers. Implementation of Boolean Expressions using transmission gates and CMOS logic. Stick diagrams and Layout of Inverter, NOR and NAND. Complex logic gates and their layouts (Euler paths). MOSIS layout design rules (full-custom mask layout designs. UNIT-4 Silicon semiconductor technology: Wafer processing, oxidation, epitaxy, | 10hrs deposition, etching, Photolithography, lon-implantation and diffusion. Silicon gate process. Chemical Vapor Deposition. Basic CMOS technology: n-well and p-well CMOS process. Silicon on insulator. Introduction to VHDL language. VHDL Programs and test benches for Adder, Subtractor, Decoder, Encoder, Multiplexer, Demultiplexer, Flip Flops, Registers and Counters. Pageaa‘TEXTBOOKS 1 | Sung-Mo (Steve) Kang, Yusuf Leblebici; CMOS Digital Integrated Circuits Analysis & Design; McGraw-Hill Education 2 | Neil Weste, David Harris; CMOS VLSI Design: A Circuits and Systems Perspective;Pearson 3_| Bhaskar; VHDL Primer; PHI 4 | Stephen Brown, Zvonco Vranesic; Fundamentals of Digital logic with VHDL design;MeGraw-Hill Education REFERENCES 1_[ Wayne Wolf; Modern VLSI design (Systems on Silicon); PHT 2 | Jan M. Rabaey; Digital Integrated Circuits - A Design perspective; Pearson Education Pageas