Testbench Build and

Connect

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How are Test benches Built?
▪ Traditional Verilog Testbenches
▪ Module based – Static Components
▪ Simulator deals with evaluations
▪ Tests/Stimulus uses always/forever blocks to
stimulate (mix of time/no-time consuming methods)
▪ Class Based SystemVerilog Testbenches
▪ Testbench Components are Dynamic
▪ These needs to be instantiated after loading up
simulator
▪ Need to define the order of building and connecting
Testbench components
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OVM/UVM Build and Connect

▪ Before applying stimulus in OVM/UVM based test

bench
▪ All Verification components and hierarchy need to be
built
▪ Connection between components needs to be made

▪ Construction is done top down

▪ Each layer of hierarchy will build components in bottom
layer

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OVM/UVM Test bench Build

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Testbench Build

▪ All uvm_component_class objects in Testbench

hierarchy constructed top down
▪ Build() method in uvm_test gets called first and
then propagates down to
env/agent/driver/sequencer etc
▪ During build() – each layer can set up
configuration database with configuration objects
that can be referenced by downstream layer
▪ For a given Block/Chip environment - build() flow
will remain mostly same.
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Example Build Flow

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Example Build Flow

▪ Test class build method gets called first which builds env class
▪ Simplest example with no config objects
▪ https://github.com/VerificationExcellence/UVMReference/b
lob/master/course_examples/simple_build_test.svh
▪ Example build using config objects
▪ https://github.com/VerificationExcellence/UVMReference/b
lob/master/course_examples/simple_build_config_eg.svh

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Build and Config

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Building Next Level Hierarchy

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Adding Virtual Interface

▪ Virtual interface is assigned to physical interface at

test top module before test::run_test() is called
▪ A handle is passed into test using
uvm_config_db::set() method
▪ Any env/agent/component can then do a
uvm_config_db::get() to get the virtual interface
needed for accessing signals

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DUT-TB Communication

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Test bench top

▪ https://github.com/VerificationExcellence/UVMRefere
nce/blob/master/course_examples/simple_tb_top_eg.
svh

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