What is OVM/UVM ?

• OVM - Open Verification Methodology

– Backward compatible with AVM and URM
• UVM - Universal Verification Methodology
– Accellera standard
– SystemVerilog UVM Base Class Library (BCL)
– Near-backward compatible with OVM

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What is OVM/UVM ?

• Both are Open source (Apache licence)

• Test benches for (System)Verilog / VHDL / SystemC
designs
• SystemVerilog class library

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OVM/UVM Conceptual View

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Highlights of OVM and UVM

▪ Constrained random, coverage-driven verification

▪ Configurable, flexible, test benches
▪ Vertical and Horizontal reuse
▪ Separation of tests/stimulus from test bench

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Highlights of OVM and UVM

▪ Transaction-level communication (TLM)

▪ Layered sequential stimulus
▪ Standardized messaging
▪ Register layer (Newly added in UVM)
▪ Enables programming and verifying registers in a
consistent and efficient manner

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UVM – OVM - Differences

▪ UVM is based on OVM 2.1.1

▪ The deprecated features from OVM were removed
in UVM (deprecated.txt file in the OVM install area).
▪ The URM and AVM compatibility layers were
removed from UVM.

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 UVM – OVM - Differences

▪ Updates in UVM
▪ Enhancements to the OVM callback facility, including
a new message catching facility.
▪ Enhancements to the OVM objection mechanism.
▪ These enhancements introduce some minor backward
incompatibilities to the OVM callback facility.
▪ Other than this – it is a blind change from ovm_* to
uvm_* for the whole library
▪ UVM continues to evolve – 1.1 to 1.2 ->

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