Name: Debjani Banerjee

Class Roll No.: CSE/19/013

Date of Experiment: 06/01/2021

Date of Submission: 20/01/2021

Experiment No.: 8(a)

Title: Cascade two RAM ICs for Vertical Expansion

Circuit Diagram:

RAM Vertical Expansion (using IC 7489 and IC 7404)

Observation Table:

WE=Low

Address Input Data Input

A4 A3 A2 A1 A0 D3 D2 D1 D0
1 0 0 0 0 1 1 0 0
1 0 0 1 0 1 1 1 0
0 0 0 1 1 1 0 1 0

WE=High

Address Input Data Output

A4 A3 A2 A1 A0 D3 D2 D1 D0
1 0 0 0 0 0 0 1 1
1 0 0 1 0 0 0 0 1
0 0 0 1 1 0 1 0 1