Princess Sumaya University

for Technology

The King Abdullah II School for Electrical

Engineering

Electronics Engineering Department

Electronics Lab.
(EE3338)

Prepared By:

Eng. Eyad Al-Kouz

Oct., 2010
 Electronics Lab. (EE 3338)

There is a quotation that I have seen, which I

am told was originally stated by Confucius. I
present it here as a very practical statement on
how the human mind approaches the learning
process:

I hear, and I forget.

I see, and I remember.
I do, and I understand.

One of the best ways to understand something

is to get your hands on it and actually
experiment with it. In electronics, this means
putting small circuits together, powering them
up, and seeing first hand what they do.
Table of Contents:

Exp. No. Experiment Title:

1 The Diode Characteristics.

2 Diode Circuits:
I. Small-Signal Diode.
II. Large-Signal Diode.

3 BJT Amplifiers (1):

I. Common Base Amplifier.
II. Common Collector Amplifier.

4 BJT Amplifiers (2):

Common Emitter amplifier

5 Op-Amp Circuits and Application:

I. Basic Op-Amp Circuits.
II. Op-Amp Application.

6 Frequency Response of CE Amplifiers:

7 Multistage Amplifier:
I. Multistage Amplifier
II. Frequency Response of Multistage Amplifier.

8 Direct Coupled Multistage Amplifier

9 JFET Biasing & Amplifiers.

 10 Differential Amplifier.

Experiment (1):

DIODE CHARACTERISTICS
1.1 Reference

Sections 3.2-3.4, Electronic Devices and Circuits: The Diode as a Nonlinear Device, AC
and DC Resistance, Analysis or DC Circuits Containing Diodes.

1.2 Objectives

1. To become familiar with checking diodes using volt-ohm meters.

2. To investigate the forward and reverse-biased characteristics of diodes.
3. To learn how to determine the dc and ac resistance or a diode.

1.3 Discussion

A diode is a semiconductor device that conducts current much more readily in

one direction than in the other. The voltage across the diode terminals determines
whether or not the diode will conduct. If the anode is more positive than the cathode, the
diode will conduct current and is said to be forward-biased. If the cathode is more
positive than the anode, the diode will conduct only an extremely small leakage current
and is said to be reverse-biased.

When forward-biased, the voltage drop across a typical silicon diode is about
0.7V (germanium diodes drop about 0.3V). At forward voltages below this threshold, the
diode only permits a small current to flow. This threshold is known as the knee of the
diode characteristic curve. Since the relationship between voltage across and current
through the diode changes in this region, the diode's resistance changes. The following
formula is used to calculate the dynamic or ac resistance of the diode:

Where:
Δ V: is the small change in voltage across the diode
Δ I: is the corresponding change in current through the diode

The static or dc resistance at any point along the characteristic curve is calculated
using Ohm's law:
 Where:
V: is the voltage across the diode
I: is the current through the diode

These relationships can be seen in the following characteristic curve diagram

shown in figure 1.1:

Figure 1.1

1.4 Procedure

1. To investigate the forward-biased characteristics of the diode, connect the following

circuit shown in figure 1.2:

Figure 1.2

2. Measure and record in Table 1.1, the diode voltage VD and the voltage VR across the
resistor for each increment of E.
3. To investigate the reverse-biased characteristics of the diode, connect the following
circuit shown in fig.3.1:

4. Measure and record in Table 1.2 the diode voltage VD for each decrement of E.

Figure 3.1

1.5 Questions

1. Calculate and record the current values in Table 1.1; calculate the voltage VR across
the resistor and current values I in Table 1.2.

2. Using the values obtained for I and VD in Table 1.1, graph the forward I-V
characteristic curve of the diode. Plot I on the vertical axis and VD on the horizontal axis.

3. Determine the static resistance of the diode at 0.1V, 0.5V, and 0.6V using the values
obtained for I and VD from Table 1.1.

4. Graphically determine the dynamic resistance of the diode at 0.1 V, 0.5V, and 0.6V
using the I-V characteristic curve obtained in question 2.

5. Using the values obtained for I and VD from Table 1.2, calculate the static resistance of
the diode at -10V.
 Table 1.1

E (Volts) VD (Volts) VR (Volts) I = VR/R

0.0

0.1

0.2

0.3

0.4

0.7

1.0

1.5

2.6

Table 1.2

E (Volts) VD (Volts) VR = E - VD I = VR/R

(Volts)

0.0

6.0-

11-

16-

21-

27-
Experiment (2): Diode Circuits

I. SMALL-SIGNAL DIODE CIRCUITS

2. I.1 Reference

Section 3.5, Electronic Devices and Circuits: Analysis of Small-Signal Diode Circuits.

2. I.2 Objectives

1. To determine the quiescent (Q) point of a small-signal diode circuit.

2. To analyze a small-signal diode circuit graphically and analytically.

2. I.3 Discussion

Small-signals are those whose total peak-to-peak variation is only a fraction of

the dc component. In small-signal diode circuits, the changes in current and voltage occur
over a very small portion of the characteristic curve of the diode. The diode is operated in
its forward-biased region, which is only linear above the knee or the characteristic. (In the
linear region, a small change in diode voltage yields a large change in diode current). In
order to use the linear portion of the diode's characteristic, the small-signal is added to a
dc voltage which shifts the operating region past the knee of the characteristic.

The following equation is used to find the current in a diode circuit having a
series resistance:

Where:
E: is the applied dc voltage
I: is the current through the diode
R: is the series resistance
VD: is the voltage across the diode

This is the equation of a line, commonly called the dc load line. Every possible
combination or current I and voltage VD is a point which lies on this line. The quiescent
current and voltage correspond to the point of intersection of the characteristic curve and
the load line. The name load line comes from the fact that the slope of the line is
inversely proportional to the series resistance, or load, in the circuit.
 Figure 2.I.1 shows how the load line is altered when the input voltage has a small
ac component. When the ac component is zero, the diode current and voltage have their
quiescent values, IQ and VQ.

Figure 2.I.1

The ac resistance rD of the diode is the reciprocal of the slope of the characteristic
at the Q point.

Where:
ΔVD: is the change in diode voltage
ΔI: is the change in diode current

The total diode current and diode voltage can be calculated analytically using the
following equations (assuming 0 .7V voltage drop across the diode):

Where:
id(t): is the ac component of the diode current
Asinωt: is the applied ac source voltage
2. I.4 Procedure
1. Connect the following small-signal diode circuit shown in figure 2.I.2:

Figure 2.I.2

2. To measure the quiescent values, or dc components, of the diode current and voltage,
set e(t) = 0V by replacing the generator with a short circuit to ground. Measure and
record the dc diode voltage VD and the dc resistor voltage VR. The quiescent diode
current can then be calculated using the relationship IQ = VR/R.

3. Reconnect the signal generator and set e(t) to 500mVp-p@1kHz. Using an

oscilloscope set for ac input coupling, observe and accurately sketch the ac component of
the voltage VD(t) across the diode.

4. To measure the ac voltage VR(t) across the resistor, it is necessary to interchange the
diode and the resistor as shown in figure 2.I.3:
 Figure 2.I.3

5. Using an oscilloscope set for ac input coupling, observe and accurately sketch the ac
component or the voltage VR(t) across the resistor. Having measured VR(t), the ac
component i(t) of the total diode current iD(t) can be calculated using the relationship
.

2. I.5 Questions

1. Determine the equation for the dc load line of the circuit in figure 2.I.2 and plot it on
the I-V characteristic. Note the quiescent point Q where the load line intersects the
characteristic curve. Compare this graphically obtained Q point with the measured Q
point from procedure step 2.

2. Using the measurements of procedure steps 2 and 5, write an expression for the total
diode current iD(t).

3. Using figure 2.I.1 as a guideline, draw the peak (maximum and minimum) ac load
lines on the diode characteristic. Now draw the ac component of the diode voltage VD(t)
and determine the resulting current iD(t). Compare the graphically obtained iD(t) with the
results obtained analytically in question 2.
Experiment (2): Diode Circuits

II. LARGE-SIGNAL DIODE CIRCUITS

2. II.1 Reference

Section 3.6, Electronic Devices and Circuits: Analysis of large-Signal Diode Circuits.

2. II.2 Objectives

1. To investigate the operation of half-wave rectifiers.

2. To demonstrate the function of diodes in basic logic circuits.

2. II.3 Discussion

Large-signal diode circuits are those in which the current and voltage variations
occur over a large range of the diode's characteristic, extending from the forward-biased
region into the reverse-biased region. Thus, in large-signal circuits, diode operation is not
confined to the linear region. This means that the diode resistance changes from a very
low value to a very high one. Consequently, the diode acts very much like a switch.

One or the most important applications of the diode in large-signal circuits is to

perform rectification, by which an alternating current is changed to a direct current. Thus,
load current will flow in one direction only. It is important to note, however, that the
diode will drop about 0.7V of the voltage applied to the circuit containing it. Therefore,
the applied voltage must be greater than 0.7V in order for any current to flow through the
load. A half-wave rectifier with graphs of applied voltage and resulting current is shown
in figure 2.II.1.
 Figure 2.II.1

Another important application of large signal diode circuits is that of performing

digital logic functions. Digital logic gates are circuits which perform logical functions
such as AND or OR. In the AND function, the output is true (a high voltage) only if both
inputs are true. In the OR function the output is true if either input is true. In a typical
logic circuit, an AND gate produces a 5V output only if inputs 1 and 2 are both 5V. The
OR gate produces a 5V output if either input 1 or input 2 is 5V.

2. II.4 Procedure

1. To investigate the use of a diode in half-wave rectifier circuits, connect the circuit
shown in fig. 2.II.2:

Figure 2.II.2

2. With a dual-trace oscilloscope set for dc input coupling, measure the peak-to-peak
values of the input voltage e(t) and the output voltage VR(t). Sketch both waveforms.

3. Reverse the diode terminals in figure 2.II.2 and repeat procedure steps 2.

4. Change the input signal e(t) in figure 2.II.2 to a 5Vp-p square wave and repeat
procedure step 2.

5. To investigate the use of diodes in simple digital logic gates, connect the following
circuit shown in figure 2.II.3:
 Figure 2.II.3

6. Measure and record the values of VO at each of the combinations of values of V1 and
V2 in Table 2.II.1.
7. To investigate another useful logic gate, connect the following circuit shown in figure
2.II.4:

Figure 2.II.4

8. Repeat procedure step 6 for the values in Table 2.II.2 and the circuit of figure 2.II.4.

2. II.5 Questions

1. Using the results of procedure step 2, calculate the peak-to-peak values of the current
i(t) and sketch its waveform.

2. Repeat question 1 for the results of procedure step 3.

3. Calculate the peak-to-peak values of the current waveform i(t) in the circuit of
procedure step 4 and sketch its waveform.

4. For each set of voltages V1 and V2 in Tables 2.II.1 and 2.II.2 determine whether each
of the diodes D1 and D2 is forward or reverse-biased. Calculate VO, assuming that each
diode has a forward-biased voltage drop of 0.7V. Compare the calculated values of VO
with the measured values.

5. What digital logic function is performed by the circuit in figure 2.II.3, and figure
2.II.4?
 Table 2.II.1

V1 (Volts) V2 (Volts) VO(Volts)

0 0

0 5

5 0

5 5

Table 2.II.2

V1 (Volts) V2 (Volts) VO(Volts)

0 0

0 5

0
5

5 5
Experiment (3): BJT Amplifiers (1)

I. COMMON BASE AMPLIFIER

3. I.1 Reference

Sections 5.1, 5.3, and 5.6, E1ectronic Devices and Circuits: Amplifier Fundamentals,
Amplifier Analysis using Small-Signal Models.

3. I.2 Objectives

1. To investigate the common base amplifier using voltage-divider bias.

2. To measure the open-circuit voltage gain, loaded voltage gain, input resistance, and
output resistance of the common base amplifier.
3. To evaluate the common base amplifier using the small-signal equivalent model.

3. I.3 Discussion

Although it has a small input resistance, the common base amplifier can be used
in some applications requiring high voltage gain. As will be demonstrated in a later
experiment, the common base amplifier is also used in conjunction with FET amplifiers
for high frequency amplification.

When used as a small-signal amplifier; the input and output voltages and currents
vary over a small range of the transistor's characteristic curves. In this situation, the
amplifier is said to be operating in its Linear region, i.e. the gain of the amplifier is the
same for all amplitude variations at the input and output.

Small-signal amplifiers are often analyzed using ac equivalent circuits.

Figure 3.I.1 shows the small-signal ac equivalent circuit of the common base amplifier in
figure 3.I.3. Notice that no capacitors or dc voltage sources appear in the equivalent
circuit, because they are assumed to be short-circuits to the ac signal. R1 and R2 in figure
3.I.3 are similarly shorted to ac ground.

The ratio of output voltage to input voltage when the amplifier is not loaded
(RL= ∞, or open) is called the open-circuit voltage gain. The open-circuit voltage gain of
the common base amplifier can be calculated using the following equation:
 Where:
RC: is the external collector resistor
rc: is the internal collector resistance
RE: is the external emitter resistor
re: is the internal emitter resistance:
Where:
IE: is the dc emitter current

Figure 3.I.1

The input resistance rin(stage) of the common base amplifier is the ac resistance
looking into the input of the amplifier stage. As can be seen in figure 3.I.1:

The output resistance ro(stage) of the common base amplifier is the ac resistance
looking back into the output of the amplifier stage. As can be seen in figure 3.I.1:

When a load resistor RL is connected across the output and a real signal source is
connected to the input, voltage divisions take place at both the input and output.
Therefore, the voltage gain from source to load is calculated as follows:

Where:
rS: is the internal resistance of the signal source

3. I.4 Procedure
1. To measure the open-circuit voltage gain, Av, and the output resistance, rO(stage) of a
common base amplifier, connect the circuit in figure 3.I.2. Measure the dc voltage across
RE. This value will be used to determine the bias current: IE = VE/RE, and the internal
emitter resistance: re ≈ 0.026/IE.

Figure 3.I.2

2. With the signal generator's frequency set to 10 kHz, and VS = 20mVp-p. Measure and
record the peak-to-peak output voltage VO (including the phase relationship between Vin
and VO). The open-circuit voltage gain AV is VO/Vin.

3. To measure the output resistance, ro(stage) of the common base amplifier, connect a 10kΩ
potentiometer connected as a rheostat between the output coupling capacitor and ground.
Adjust this potentiometer until VO is (one-half of the previous output). Remove the
potentiometer and measure its resistance. By the voltage divider rule, this resistance
equals the output resistance of the common base amplifier.

4. To measure the loaded voltage gain from source-to-load, VL /VS, of the common base
amplifier, connect the circuit shown in figure 3.I.3.

Figure 3.I.3
5. With the signal generator's frequency set to 10 kHz, and VS = 20mVp-p. Measure and
record the peak-to-peak output voltage VL and the phase relationship between Vin and VL.
The voltage gain from source to load is VL /VS.

6. Reconnect the circuit of figure 3.I.3. Now increase the amplitude of the signal source
until the output voltage VL starts to distort. Measure the peak-to-peak value of the output
voltage at the point where it just starts to distort.

3. I.5 Questions

1. Using the measurements made in procedure step 1, calculate the quiescent current IE,
and the internal emitter resistance re.

2. Using the values obtained in question 1, and assuming that the internal collector
resistance is infinite, draw the small-signal ac equivalent circuit for the amplifier of figure
3.I.3.

3. Using the equivalent circuit from question 2, calculate the theoretical values for AV,
VL/VS, rin(stage), and rO(stage). Compare these with the measured values.

4. Explain the distortion observed in procedure step 6. Why does the output waveform
distort when the amplitude of the input is increased above a certain value?
Experiment (3): BJT Amplifiers (2)

II. COMMON COLLECTOR AMPLIFIER

3. II.1 Reference

Sections 5.1, 5.3, and 5.6, Electronic Devices and Circuits: Amplifier Fundamentals,
Amplifier Analysis using Small-Signal Models, Improved Bias Methods for Discrete BJT
Circuits.

3. II.2 Objectives

1. To measure the open-circuit voltage gain, input resistance, and output resistance of the
common collector amplifier.
2. To evaluate the common collector amplifier using the small-signal equivalent model.
3. To demonstrate the effectiveness of the common collector as a buffer between a high
impedance source and a low impedance load.

3. II.3 Discussion

The last important small-signal amplifier configuration or the BJT is the common
collector, or emitter follower amplifier. It is extremely useful because it has very high
input resistance, high current gain, very small output resistance, and approximately unity
voltage gain. The high input resistance and low output resistance make the emitter
follower an ideal buffer between a high impedance source and a low impedance load. A
buffer is any circuit that keeps the source from being affected by a load. For example, a
common emitter amplifier with a 10kΩ output resistance could not provide very much
voltage gain to a 50Ω load resistor.

The following small-signal ac equivalent circuit that shown in figure 3.II.1 can be
used to calculate the gain, input resistance, and output resistance of the common collector
amplifier of figure 3.II.2. Note that the current-controlled current source in figure 3.II.1 is
pointing down, like that of the common emitter amplifier. However, the load in this case
is in parallel with the emitter resistor, so the output voltage is in phase with the input
voltage.

The open-circuit voltage gain, AV, of the emitter follower amplifier can be
calculated using the following equation (since RE is typically much larger than re, the
equation can be approximated as1):
 The input resistance, rin(stage) of the emitter follower amplifier can be calculated
using the following equation:

Figure
3.II.1

The output resistance, rO(stage) of the emitter follower amplifier can be calculated
using the following equation:

3. II.4 Procedure

1. Use Digital Multimeter (DMM) to measure the β's of the transistors.

2. To measure the open-circuit voltage gain, AV, of the common collector amplifier,
connect the following circuit shown in figure 3.II.2:

3. With the signal generator's frequency set to 10 kHz, and VS = 100mVp-p. Measure and
record the peak-to-peak output voltage VO and the phase relationship between Vin and
VO. These values can be used to calculate the open-circuit voltage gain, AV.
 Figure
3.II.2

3. II.5

Questions

1. Calculate the dc emitter current IE and the internal emitter resistance re for the circuit of
figure 3.II.2.

2. Using the values obtained in question 1, draw the small-signal ac equivalent circuit for
the amplifier or figure 3.II.2.

3. Using the equivalent circuit from question 2, calculate the theoretical values for AV,
rin(stage), and rO(stage).
Experiment (4): BJT Amplifiers (2)

COMMON EMITTER AMPLIFIER

4. 1 Reference

Sections 5.1, 5.3, and 5.6, Electronic Devices and Circuits: Amplifier Fundamentals,
Amplifier Analysis using Small-Signal Models, Improved Bias Methods for Discrete BJT
Circuits.

4. 2 Objectives

1. To measure the open-circuit voltage gain, loaded voltage gain, input resistance, and
output resistance of the common emitter amplifier.
2. To evaluate the common emitter amplifier using the small-signal equivalent model.
3. To demonstrate the differences in voltage gain and input resistance due to the removal
of the emitter bypass capacitor.

4. 3 Discussion

The most important BJT small-signal configuration is the common emitter

amplifier. It is extremely useful because it has high voltage gain, high current gain,
moderate input resistance and moderate output resistance. The common emitter amplifier
will be used as the example in most general amplifier experiments in this book.

In many common emitter amplifiers, the emitter resistor is bypassed, by

connecting a capacitor in parallel with it. At high frequencies, the capacitor effectively
shorts the emitter resistor to ground, but at dc the capacitor is large impedance that does
not affect the dc biasing of the circuit. The purpose of the emitter bypass capacitor is to
increase the gain of the amplifier by eliminating ac degeneration. AC degeneration occurs
when there is a voltage present across the emitter resistor that is out of phase with the
output voltage.

The small-signal ac equivalent circuit in figure 4.1 can be used to calculate the
gain, input resistance, and output resistance of the common emitter amplifier of
figure 4.3. The equivalent circuit does not show RE because it is assumed to be
completely bypassed (shorted to ground) by CE at the frequency of operation. Note that
the current-controlled current source in figure 4.1 is pointing down, unlike that of the
common base amplifier. This means that the output voltage is negative with respect to the
input voltage, corresponding to a 180° phase shift. For this reason the common emitter
amplifier is referred to as an inverting amplifier.
 The open-circuit voltage gain AV of the common emitter amplifier can be
calculated using the appropriate one of the following equations (the minus sign means
that the common emitter amplifier is an inverting amplifier):

With RE bypassed:

With RE unbypassed:

Figure 4.1

The input resistance rin(stage) of the common emitter amplifier can be calculated
using the appropriate one of the following equations:

With RE bypassed:
With RE unbypassed:

The output resistance, rO(stage) of the common emitter amplifier can be calculated
using the following equation:

The loaded voltage gain from source-to-load VL/VS can be calcu1ated using the
following equation:
4. 4 Procedure

1. Use Digital Multimeter (DMM) to measure the β of the transistor.

2. To measure the open-circuit voltage gain AV of the common emitter amplifier, connect
the following circuit in figure 4.2:

Figure 4.2

3. With the signal generator's frequency set to 10 kHz, and VS = 20mVp-p. Measure and
record the peak-to-peak output voltage VO and the phase relationship between Vin and
VO. The open-circuit voltage gain AV is VO/Vin.

4. To measure the voltage gain from source-to-load, VL/VS of the common emitter
amplifier, connect the circuit in figure 4.3.

5. With the signal generator's frequency set to 10 kHz, and VS = 50mVp-p. Measure and
record the peak-to-peak output voltage VL and the phase relationship between Vin and VL.
The voltage gain from source to load is VL /VS.

6. Disconnect the emitter bypass capacitor CE from the circuit shown in figure 4.3 and
repeat procedure steps 3, and 5.
 Figure 4.3

4. 5 Questions

l. The theoretical dc emitter current, IE, in a circuit biased like that shown in figure 4.3
can be calculated as follows: First, the base-to-ground voltage VB is determined using the
voltage divider rule: . Then, the dc emitter-to-ground voltage, VE,

equals VB minus the drop across the base-emitter junction: .

Finally, . Calculate the theoretical values of IE and re in figure 4.3.

2. Using the values obtained in question 1, and assuming that the internal collector
resistance rc is infinite, draw the small-signal ac equivalent circuit for the amplifier of
figure 4.3.

3. Using the equivalent circuit from question 2, calculate the theoretical values for AV,
VL/VS, rin(stage), and rO(stage).

4. Calculate the theoretical values for AV, VL/VS, rin(stage), and rO(stage) for the circuit which is
the same as figure 4.3 with the emitter bypass capacitor removed.
5. What are the advantages and disadvantages of an emitter bypass capacitor (in terms of
gain and input impedance)?
Experiment (5): Op Amp Circuits & Applications

I. BASIC OP AMP CIRCUITS

5. I.1 Reference

Williams, Gerald E., Analog Electronics: Devices, Circuits, and Techniques, Chapter 8.
Minneapolis/St. Paul. West Publishing Company, 1996.

5. I.2 Objectives

1. To study the ac characteristics of the non-inverting op amp configuration.

2. To study the ac characteristics of the inverting op amp configuration.
3. To observe the 180° phase shift associated with the inverting op amp configuration.

5. I.3 Discussion

The basic non-inverting op amp configuration is shown in figure 5.I.1. The

operational amplifier itself, within the triangle, has a very large open loop voltage gain, a
reasonably high Rin and a fairly low RO.

These are all desirable characteristics. Resistors Rl and R2 are feedback resistors
which generally improve the amplifier's characteristics at the expensive of voltage gain.
At the same time, the voltage gain is stabilized to a particular value, which is also a
desirable characteristic.

Figure 5.I.1

The op amp with feedback will have characteristics determined mostly by the two
external resistors. The characteristics of the non-inverting op amp are given in equations
5.I.1, 5.I.2 and 5.I.3.
 Sometimes an additional resistor is connected from (+) to ground in order to set
the input resistance to a specific value. A very common configuration of the non-
inverting op amp is the "buffer" amplifier used to isolate stages. The buffer is made by
replacing R2 in figure 5.I.1 with a short circuit, and replacing Rl with an open circuit.
Equation 5.I.3 will show that this will provide a voltage gain of exactly one.

Figure 5.I.2 illustrates the basic inverting op amp configuration.

Figure 5.I.2

Again, the characteristics are determined largely by the external biasing resistors.
The characteristics of the inverting op amp are given in Equations 5.I.4, 5.I.5 and 5.I.6.

5. I.4 Procedure

 Non-Inverting Amplifier Measurements

1. Connect the circuit of figure 5.I.3 using an 8-pin LM741 op amp.

2. Using a 180kΩ sensing resistor, complete the amplifier measurements required for
Table 5.I.1. Use a generator frequency of 1kHz.
 Figure 5.I.3

Table 5.I.1. Amplifier Measurements

Vg Vin VOC VO

100mVp-@1kHz

3. Using the data measured in Table 5.I.1, calculate the amplifier characteristics required
for Table 5.I.2.

Table 5.I.2. Amplifier Calculations

Ii IO Rin RO

AVO AV Ai AP Units

None

dB

4. Check the input signal and the output signal simultaneously to make sure that there is
0° phase shift in this amplifier.
  Inverting Amplifier Measurements
5. Connect the circuit of figure 5.I.4. Using an 8-pin LM741 op amp.

Figure 5.I.4

6. Using a 39kΩ sensing resistor, complete the amplifier measurements required for
Table 5.I.3. Use a generator frequency of 1kHz.

Table 5.I.3. Amplifier Measurements

Vg Vin VOC VO

100mVp-@1kHz

7. Using the data measured in Table 5.I.3, calculate the amplifier characteristics required
for Table 5.I.4.

Table 5.I.4. Amplifier Calculations

Ii IO Rin RO

AVO AV Ai AP Units

None

dB
8. Check the input signal and the output signal simultaneously to make sure that there is
180° phase shift in this amplifier.

5. I.5 Questions

1. Refer to Table 5.I.1. Explain why the measurements of VOC and VO are the same,
within measurement accuracy.

2. Calculate the theoretical Ri, RO and AV for the circuit of figure 5.I.3 and compare these
values to those determined from measurements.

3. Calculate the theoretical Ri, RO and AV for the circuit of figure 5.I.4 and compare these
values to those determined from measurements.
Experiment (5): Op Amp Circuits & Applications

II. OP AMP APPLICATIONS

5. II.1 Reference

Sections 14.1 and 14.3, Electronic Devices and Circuits: Voltage Summation,
Subtraction, and Scaling; Integration, Differentiation, Wave shaping.

5. II.2 Objectives

1. To demonstrate the use of operational amplifiers for performing mathematical

operations-summation, integration, and differentiation.

5. II.3 Discussion

When the first operational amplifiers were constructed, their primary function was
to perform mathematical operations in analog computers. These included summation,
subtraction, multiplication, division, integration, and differentiation. Figure 5.II.2 shows
an example of how an operational amplifier is connected to perform voltage summation.
(In this figure, an ac and a dc voltage are summed). In general:

As shown in figure 5.II.1, the output of an electronic integrator is proportional to

the total area under the input waveform up to that point in time. To perform integration, a
capacitor is connected in the feedback path of the amplifier. However, any dc voltage
appearing at the input of an integrator will cause the output voltage to rise (or fall) until it
reaches its maximum possible value. To prevent this undesirable occurrence, a resistor,
RF, is connected in parallel with the feedback capacitor. Any dc input voltage, such as the
input offset voltage of the amplifier, is then simply amplified by the dc gain, RF/R1.

Figure 5.II.1
 The following equation can be used to determine the output voltage of the
operational amplifier integrator with a sine wave input:

Integration will be performed only at frequencies well above the break frequency
caused by the feedback resistor:

As shown in figure 5.II.1, the output of an electronic differentiator is proportional

to the rate of change of the input waveform at any point in time. To perform
differentiation, a capacitor is connected in series with the input. The following equation
can be used to determine the output voltage of the operational amplifier differentiator
with a sine wave input:

Since the output voltage or a differentiator is proportional to the input frequency,

high frequency signals (such as electrical noise) may saturate or cutoff the amplifier. For
this reason, a resistor is placed in series with the capacitor in the input. This establishes a
high frequency limit beyond which differentiation no longer occurs:

To achieve greater attenuation at higher frequencies (to prevent oscillation), a

feedback capacitor is added in parallel with the feedback resistor. This establishes
another break frequency that can be calculated as in the integrator.

5. II.4 Procedure

1. To demonstrate the use of an operational amplifier as a summing amplifier, connect the

following circuit shown in figure 5.II.2:

Figure 5.II.2
2. With VS adjusted to produce a 2Vp-p sine wave at 1kHz, observe the output voltage VO
on an oscilloscope set to dc input coupling. Sketch the output waveform. Be sure to note
the dc level in the output.

3. Interchange the 5V dc power supply and the 2Vp-p signal generator. Repeat procedure
step 2.

4. To investigate the use of an operational amplifier to perform mathematical integration,

connect the following circuit shown if figure 5.II.3:

5. With VS adjusted to produce a 10Vp-p sine wave at 20Hz, and using a dual-trace
oscilloscope set to ac input coupling, measure and record the peak value of the output
voltage VO in Table 5.II.1. Note any phase shift of the output voltage VO with respect to
the input voltage VS. Repeat this procedure for the remaining frequencies in Table 5.II.1.

Figure 5.II.3

6. Set VS to a 10Vp-p square wave at 100Hz. Using a dual-trace oscilloscope, sketch the
output voltage VO with respect to the input voltage VS.

7. To demonstrate the use of an operational amplifier as a differentiator, connect the

following circuit shown in figure 5.II.4:

8. With VS adjusted to produce a 2Vp-p sine wave at 500Hz, and using a dual-trace
oscilloscope set to ac input coupling, measure and record the peak value of the output
voltage VO in Table 5.II.2. Note any phase shift of the output voltage VO with respect to
the input voltage VS. Repeat this procedure for the remaining frequencies in Table 5.II.2.
 Figure5.II.4

9. Set VS to a 2Vp-p square wave at 200Hz. Using a dual-trace oscilloscope, sketch the
output voltage VO with respect to the input voltage VS.

Table 5.II.1

Frequency (Hz) Vo (Volts) Phase Shift

20

50

100

500

1k

Table 5.II.2

Frequency (Hz) Vo (Volts) Phase Shift

500

200

100
5. II.5 Questions

1. Write the theoretical equation for the output voltage in the circuit of figure 5.II.2 with
the input voltages prescribed by procedure steps 2 and 3. Compare these equations with
the equations based on the measurements obtained in procedure steps 2 and 3.

2. Write the theoretical equation for the output of the integrator circuit of figure 5.II.3 for
each of the input frequencies in Table 5.II.1. Compare these with the equations based on
experimental voltage measurements obtained in procedure step 5. Explain any phase shift
of the output voltage with respect to the input voltage.

3. Repeat question 2 for Table 5.II.2, and the measurements obtained in procedure step 8.

5. Did the results of procedure step 6 and 9 verify a integrator’s and differentiator's
response to a square wave input? What differences, If any, were there between the
sketches obtained in procedure step 6 and 9 and figure 5.II.1?

6. Calculate the theoretical break frequencies for both the integrator of figure 5.II.3, and
the differentiator of figure 5.II.4.
Experiment (6):

FREQENCY RESPONCE OF AMPLIFER

6. 1 Reference

Sections 10.1-10.3, 10.6, Electronic Devices and Circuits: Definitions and Basic
Concepts, Decibels and Logarithmic Plots, Series Capacitance and Low Frequency
Response, Frequency Response or BJT Amplifiers.

6. 2 Objectives

1. To measure the lower cutoff frequency of a common emitter amplifier.

2. To measure the lower cutoff frequencies due to each coupling and bypass capacitor.
3. To measure the upper cutoff frequency of a common emitter amplifier.
4. To measure the upper cutoff frequencies due to shunt capacitances.

6. 3 Discussion

Since the impedance of coupling capacitors increase as frequency decreases, the

voltage gain or a BJT amplifier decreases as frequency decreases. At very low
frequencies, the capacitive reactance of the coupling capacitors may become large
enough to drop some of the input voltage or output voltage. Also, the emitter bypass
capacitor may become large enough that it no longer shorts the emitter resistor to ground.

The following equation can be used to determine the lower cutoff frequency,
where the voltage gain drops 3dB from its mid-band value (0.707 times the mid-band
AV):

Where:
f1(C1) = lower cutoff frequency due to C1
C1 = input coupling capacitance
rin(stage) = input resistance of the amplifier
rS = source resistance

Where:
f1(C2) = lower cutoff frequency due to C2
C2 = output coupling capacitance
 rO(stage) = output resistance of the amplifier
RL = load resistance

Where:
f1(CE) = lower cutoff frequency due to CE
CE = emitter bypass capacitance
rTH = Thevenin resistance parallel to the capacitor:

Where:
RB = parallel combination of all the input bias resistors

Provided that f1(C1), f1(C2), and f1(CE) are not close in value, the actual lower
cutoff frequency is approximately equal to the largest of the three.

The capacitive reactance of a capacitor decreases as frequency increases. This fact

can lead to problems when an amplifier is used for high-frequency amplification. A
transistor has inherent shunt capacitances between each pair of its terminals. At high
frequencies, these capacitances effectively short (shunt) the ac signal voltage. Therefore,
in high-frequency amplifiers, shunt capacitance must be extremely small.

In this experiment, artificial shunt capacitors will be installed in the amplifier

circuit because it is extremely difficult to measure the actual interelectrode capacitances
of the transistor. It is equally difficult to measure stray shunt-capacitance due to the
wiring of the circuit. Since the artificial capacitors are much larger than the real
capacitance already present, the parallel combination of real capacitance and artificial
capacitors is approximately equal to the value of the artificial capacitors.

The objective is to investigate the high frequency response of the amplifier to gain
insight into the problems associated with shunt capacitance, and to obtain practice
measuring the upper cutoff frequency of an amplifier.

The upper cutoff frequency is the larger of the two frequencies where the voltage gain of
the amplifier is -3dB or 0.707 times the mid-band value (the lower cutoff frequency is the
other frequency where this occurs).

6. I.4 Procedure

1. Use the DMM to measure the β of the transistor.

2. To measure the low frequency response of the common emitter amplifier, connect the
following circuit shown in figure 6.1:
The plus (+) signs show the polarities or the electrolytic capacitors used in procedure-
steps 5-8):

Figure 6.1

3. With VS = 50mV p-p@10kHz, measure and record VL. This value can be used to
determine the mid-band voltage gain VL/ VS.

4. Now decrease the frequency of the signal generator to each frequency in Table 6.1
measuring the value of VL at each frequency. Make sure the output voltage from the
signal generator is constant. These values will be used to plot the low frequency response
of the amplifier.

5. By making two capacitors very large, the effects of those capacitors on the lower
cutoff frequency can be made negligible. The cutoff frequency due to the third capacitor
can then be measured. With this in mind, reconnect the circuit of figure 6.I.1 with the
following capacitor values (observe polarities as shown in figure 6.1):

C1= 0.1μf, C2 = 100μf, CE 100μf.

6. Making certain that VS remains at 50mVp-p, adjust the frequency of the signal
generator until the output voltage (and therefore the voltage gain) equals 0.707 times that
measured in procedure step 3. The frequency where this occurs is f1(C1).

7. Repeat procedure steps 5 and 6 to determine f1(C2), using the following capacitor
values:
C1 = 100μf, C2=0.22μf, CE= 100μf
8. Repeat procedure steps 5 and 6 to determine f1(CE), using the following capacitor
values:
C1=100μf, C2=100μf, CE=4.7μf

6. 5 Questions

1. Using the results obtained of step 1, of the β of the transistor. Determine re. Then use
these values to calculate the mid-band ac parameters of the circuit in figure 6.1 ( rin(stage),
rO(stage) , VL /VS).

2. Calculate the values for VL /VS at each frequency in Table 6.1. Then plot these values
on log-log graph paper. Include asymptotic lines which show the break frequency due to
each capacitor. From this graph of frequency response, obtain the lower cutoff frequency
(-3dB point) and label the graph accordingly.

3. Ca1culate f1(C1), f1(C2), and f1(CE) for the common emitter amplifier. Compare these
with the 1ower cutoff frequencies measured in procedure steps 5-8.

4. Which capacitor had the most effect on the lower cutoff frequency? Compare the lower
cutoff frequency due to this capacitor with the overall cutoff frequency determined in
question 2. Comment and explain.
 Table 6.1

Frequency VL AV=VL/VS AV(dB)

(Hz) (Vp-p) V/V =20log(AV)
50
100
200
250
500
750
900
1k
1.5k
2k
5k
7.5k
10k
20k
50k
75k
100k
250k
500k
600k
700k
750k
800k
850k
900k
950k
1M
5M
7.5M
10M
12M
Experiment (7): Multistage Amplifier

I. MULTISTAGE AMPLIFIER
7.I.1 Reference

Sections 11 .1-11.3, Electronic Devices and Circuits: Gain Relations in Multistage

Amplifiers, Methods of Coupling, RC Coupled BJT Amplifiers.

7.I.2 Objectives

1. To determine the overall voltage gain of cascaded common-emitter amplifiers.

2. To demonstrate the loading effect of cascading common-emitter amplifiers.

7.I.3 Discussion

Often in electronic amplifier systems, several amplifiers are cascaded in order to

furnish adequate gain. It is easy to see that the resulting gain of two cascaded ideal
amplifiers would be the product of the individual gains. However, since voltage sources
and amplifiers have output resistance, and amplifiers and loads have input resistance,
there are voltage divisions taking place between these stages or amplification.

Figure 7.I.1 shows a two-stage amplifier. AO1 and AO2 are the open-circuit (un-
loaded) voltage gains of each stage:

Figure 7.I.1

To calculate the overall gain of the multistage amplifiers, the product of the
individual open-circuit gains of each stage is reduced by the voltage divider at the input
and the output of each stage. The following equation can be used to calculate the overall
gain of a two-stage amplifier.

7.I.4 Procedure

1. Use DMM to measure the β's of two transistors.

2. To measure the open-circuit voltage gain of a single stage, connect the following
common emitter amplifier circuit shown in figure 7.I.2:

Figure 7.I.2

3. With the signal generator set at 50mVp-p@1kHz, measure the no-load ac output
voltage VO as well as the phase shift of the output with respect to the input. This can be
used to determine the open-circuit unloaded voltage gain AO.

4. To demonstrate the effects on overall voltage gain of cascading two common emitter
amplifiers, make the following interconnection of two identical amplifiers (stages) shown
in figure 7.I.3:

5. With the signal generator set at 50mV p-p at 1 kHz, measure the output voltage VL
across the load resistor, as well as the phase shift with respect to the input voltage VS.
 Figure 7.I.3

7.I.5 Questions

1. Using the results of step 1, calculate the input resistance rin(stage), the output resistance
rO(stage), and the unloaded voltage gain (AO) of the two individual common emitter
amplifier stages. Compare the calculated voltage gain with the actual measured voltage
gain obtained in procedure step 3.

2. Using the results of question 1, calculate the overall gain from source-to-load VL/VS.
Compare the calculated gain with that measured in procedure step 5.

3. Explain the phase relationship of the output voltage VL with respect to the input
voltage VS as observed in procedure step 5.
Experiment (7): Multistage Amplifier

II. FREQUENCY RESPONSE OF

MULTISTAGE AMPLIFIERS

7.II.1 Reference

Sections 11.1-11.3, Electronic Devices and Circuits: Gain Relations in Multistage

Amplifiers, Methods of Coupling, RC Coupled BJT Amplifiers.

7.II.2 Objectives

1. To measure the low frequency response of a two-stage common emitter amplifier.

2. To measure the lower cutoff frequency due to each coupling capacitor of the two-stage
common emitter amplifier.

7.II.3 Discussion

Whenever several amplifiers are RC coupled in order to furnish adequate gain,

there will be additional coupling capacitors affecting the lower frequency response. As
was the case with the single-stage amplifier, there is a lower cutoff frequency associated
with each coupling and bypass capacitor. The calculations for lower cutoff frequency are
the same as for the single-stage amplifier, except there are additional capacitors that must
be taken into account. In this experiment, no emitter-bypass capacitors will be used. This
will simplify the calculations for rin(stage) and VL/VS at mid-band, and it will reduce the
number of lower cutoff frequencies to be calculated.

Figure 7.II.1 shows the Thevenin equivalent of a two-stage amplifier. AO1 and
AO2 are the open-circuit (un-loaded) voltage gains of each stage. The capacitors C1, C2,
and C3 are coupling capacitors.

The following equations are used to calcu1ate the lower cutoff frequency due to
each coupling capacitor C1, C2, and C3. The lower cutoff frequency of a single-stage
amplifier:

Where:
f1(C1): is the cutoff frequency due to the input coupling capacitor
 f1(C2): is the cutoff frequency due to the coupling capacitor
between the amplifier-stages
f1(C3): is the cutoff frequency due to the output coupling capacitor

Figure 7.II.1

7.II.4 Procedure

1. Use DMM to measure the β's of two transistors.

2. To measure the low frequency response of a two-stage RC coupled amplifier, connect

the following circuit shown in figure 7.II.2 (the plus (+) signs show the polarities of the
electrolytic capacitors used in procedure steps 5-to-8):

3. With the signal generator set to 50mVp-p@15kHz, measure the ac output voltage VL.
This value can be used to determine the mid-band voltage gain from source-to-load,
VL/VS.

4. Now decrease the frequency of the signal generator until the output voltage VL is 0.707
times the level measured in procedure step 3. The frequency where this occurs is the
lower cutoff frequency of the amplifier. Make a sufficient number of measurements from
15kHz down to 50Hz as shown in Table 7.II.1 to use for graphing the low frequency
response of the amplifier.
 Figure 7.II.2

5. By making two capacitors very large, the effects of those capacitors on the lower
cutoff frequency can be made negligible. The cutoff frequency due to the third capacitor
can then be measured. With this in mind, reconnect the circuit of figure 7.II.2 with the
following capacitor values (observe polarities as shown in figure 7.II.2):

C1 = 0.1μf C2 = 100μf C3 = 100μf

6. Adjust the frequency of the signal generator until the output voltage (and therefore the
voltage gain) equals 0.707 times that measured in procedure step 3. The frequency where
this occurs is f1(C1).

7. Repeat procedure steps 5 and 6 for f1(C2), using the following capacitor values:

C1 = 100μf C2 = 0.0022μf C3 = 100μf

8. Repeat procedure steps 5 and 6 for f1(C3), using the following capacitor values:

C1 = 100μF C2 = 100μF C3 = 0.01μF

7.II.5 Questions

1. Use the values of β to calculate the ac parameters of the amplifier (rin(stage1), ro(stage1),
rin(stage2), ro(stage2). and VL/VS) of the entire two-stage common emitter amplifier.

2. Calculate the value of VL/VS for each measurement made in procedure step 4. Plot
these values on log-log paper. Add asymptotic lines to this graph and show the break
frequency due to each coupling capacitor. Use the asymptotes to verify that the gain falls
off 6dB/octave after the first break, 12dB/octave after the second, and 18dB/octave after
the third.

3. Calculate the theoretical values of fl(C1), f1(C2), and f1(C3) for the two-stage common
emitter amplifier of figure 7.II.2. Compare these with the lower cutoff frequencies
measured in procedure steps 5-8.

Table 7.II.1

Frequency (Hz) VL (Vp-p) AV=VL/VS AV (dB)

100
250
500
750
1k
5k
10k
50k
75k
100k
250k
500k
750k
1M
5M
7.5M
10M
Experiment (8):

DIRECT-COUPLED MULTISTAGE
AMPLIFIERS
8.1 Reference

Sections 11.1, 11.2, and 11.4, Electronic Devices and Circuits: Gain Relations in
Multistage Amplifiers, Methods of Coupling, Direct-Coupled BJT Amplifiers.

8.2 Objectives

1. To measure the open-circuit voltage gain of direct-coupled common emitter amplifiers.

2. To measure the open-circuit voltage gain of direct-coupled complementary common-
emitter amplifiers.
3. To demonstrate the use of direct-coupled amplifiers to amplify dc.

8.3 Discussion

In many applications a system must amplify either dc or a very low frequency

input voltage. For example, a measurement of outside temperature would show a nearly
sinusoidal variation with a positive peak in the early afternoon and a negative peak in the
early morning. A voltage waveform representing this variation would have a frequency of
about 11.6μHz. At a frequency this low, coupling capacitors would prevent any of the
waveform from passing through the amplifier. Therefore, direct-coupled amplifiers are
used.

The circuit shown in figure 8.1 is an example of a direct-coupled amplifier.

Notice that the dc collector voltage VC1 of the first stage is also the dc base voltage VB2 of
the second stage. Since the collector-to-base junction of an NPN transistor must be
reverse-biased to keep the collector voltage in the linear region of the output
characteristics, the collector voltage of Q2 must be more positive than the collector
voltage of Q1, after several stages of amplification, the collector voltage approaches the
supply voltage and the voltage swing of the output is limited.

To correct the problem of increasing collector voltages from one stage to the next,
the second stage can be changed to a complementary (PNP) device, as shown in
figure 8.2. Recall that the collector voltage of a PNP transistor must be more negative
than its base voltage. Therefore, the collector voltage of Q2 is less than the collector
voltage of Q1. Typically, direct-coupled amplifiers will consist of an NPN stage followed
by a PNP stage, etc.

For either the circuit in figure 8.1 or the circuit in figure 8.2, the no-load voltage
gain is calculated just as it is with RC coupled amplifiers. In this experiment, the large
value of RE2 in both circuits makes the loading effect of the second stage on the first
negligible. Therefore, the following approximation can be used for the circuits in figures
8.1 and 8.2 (the output voltage of the circuit in figure 8.2 will be inverted):

The following approximation can be used to calculate the loaded voltage gain
VL/VS of the circuits in figures 8.1 and 8.2:

8.4 Procedure

1. To demonstrate the direct-coupled common emitter amplifier, connect the following

circuit shown in figure 8.1:

Figure 8.1

2. Adjust the variable dc power supply connected to the base of Q1 until the input voltage,
VB1, is 1.50V dc. Measure and record all quiescent voltages on both transistors, including
VC2.

3. Increase the variable dc power supply until the input voltage VB1 is 1.60V dc. Measure
and record the corresponding voltage VC2. Decrease the variable dc power supply until
the input voltage VB1 is 1.40V dc.
Measure and record the corresponding voltage VC2. The overall voltage gain AV can be
found from ΔVC2/ ΔVB1, where Δ means the change in.

4. Connect a 10kΩ load to the circuit in figure 8.1 between the collector of Q2 and ground
and repeat procedure steps 2 and 3. The values obtained from these measurements can be
used to calculate the loaded voltage gain VL/VS.

5. To demonstrate the complementary direct-coupled common emitter amplifier, connect

the following circuit shown in figure 8.2:

Figure 8.2

6. Repeat procedure steps 2-to-4 for the circuit of figure 8.2.

8.5 Questions

1. Calculate the theoretical quiescent values of VC1 and VC2 when VBl = 1.5V in figure 8.1.
Compare these values with those measured in procedure step 2.

2. Using the change in output voltage and the change in input voltage obtained from
procedure steps 2 and 3. Calculate the overall no-load voltage gain of the circuit in figure
8.1. Compare this value to the theoretical no-load voltage gain AV, described in the
discussion section.

3. Using the results of procedure step 4, calculate the loaded voltage gain of the circuit in
figure 8.1. Compare this value to the theoretical loaded voltage gain, VL/VS, described in
the discussion section.

4. Repeat questions 1, 2, and 3 for the complementary direct-coupled amplifier in figure

8.2. Be careful to note that the emitter resistor RE2, is at the top or the figure.
Experiment (9):

JFET BIASING AND AMPLIFIERS

9.1 Reference

Williams, Gerald E., Analog Electronics: Devices, Circuits, and Techniques, Chapter 7.
Minneapolis / St. Paul. West Publishing Company 1996.

9.2 Objectives

1. To understand the techniques used to accomplish dc biasing of field-effect transistors.

2. To understand the circuits used to accomplish dc biasing of field-effect transistors.
3. To study the ac characteristics (Ri, Ro, Avo, Av, Ai and Ap) of a common-source
amplifier.
4. To similarly study the ac characteristics of a source-follower amplifier.

9.3 Discussion
9.3.1: JFET BIASING
FETs have two electrical characteristics which, within a single device number,
can vary considerably. These characteristics are the specifications for IDSS and VGS(off). For
example, a 2N5457 N-channel JFET will have an IDSS which can vary from 1.0 mA
to 5.0 mA, and an VGS(off) which can vary from -0.5V to -6.0V. This wide variation makes
it a challenge to create a circuit which will work with any 2N5457 JFET.

It is often desired to know the IDSS and VGS(off) for a specific JFET. They can be
measured using the circuit of figure 9.1. IDSS is measured in figure 9.1 (a) by measuring
the voltage directly across 1kΩ resistor, and dividing the voltage by 1kΩ. VGS(off) is
measured using figure 9.1 (b). The –VGG supply is adjusted until the voltage across 1kΩ
resistor in the drain circuit is half of what was measured when determining IDSS. The VGS
voltage is then measured directly and VGS(off) is calculated from Equation 9.1

………………………….Equation 9.1
 Figure 9.1 Circuits for Determining IDSS and VGS(off)

Figure 9.2 Source Self-Bias Circuit

A source self-bias circuit is shown in figure 9.2. To obtain a desired ID and VDS,
the equations necessary to determine the resistor values are presented below. The gate
resistor is chosen for the desired Ri, often 100kΩ.

………….......Equation 9.2

……………….. ………………Equation 9.3

… ……………….Equation 9.4
 Figure 9.3 Gate Voltage Divider Bias Circuit

A gate voltage divider bias circuit is shown in figure 9.3. To obtain a desired ID
and VDS, the equations necessary to determine the resistor values are presented below.

……….…Equation 9.5

Equation 9.6 is not carved in stone, but is presented as a rule of thumb.

……………………...Equation 9.6
………………………..Equation 9.7

…………………….……….Equation 9.8

………………..Equation 9.9
If R2 is chosen as 100kΩ, a reasonably high Ri will be obtained.
…………………..Equation 9.10

…………………..……Equation 9.11

A bias line for a source self-bias circuit is shown drawn upon the transfer curve in figure
9.4. The bias line for this circuit always starts at the origin, and has slope of (-1/RS).

Figure 9.4 Bias Line for the Source Self-Bias Circuit

The bias line is particularly useful to allow the student to predict what may happen in this
circuit if a fault occurs. For example, if RS were to decrease, the bias line would be more
vertical, thus intersecting the transfer curve higher up. This causes the drain current to
increase.

Figure 9.5 Bias Line for the Gate Voltage Divider Bias Circuit

The bias line for the gate voltage divider bias circuit in figure 9.5 is very similar. The bias
line for this circuit always start at the value of the gate voltage, and has a slope (-1/RS).
As an example of its use to predict circuit operation, consider what would happen in the
circuit if R1 were to increase in value. The gate voltage would become smaller, but since
RS is unchanged, the whole bias line would shift to the left. This would cause the bias line
to intersect the transfer curve at a lower value of drain current. So, if R1 increases, the
drain current will decrease. This, in turn, would cause the drain to source voltage to
increase.

9.3.2: JFET AMPLIFIERS

A JFET parameter which controls voltage gain in FET amplifiers is called rm. In
fact, most FET amplifier equations are almost the same as those used in BJTs, except that
β is replaced with rm. The parameter rm, is slightly more difficult to obtain than was β.
Input resistance for FETs is generally regarded as infinite, consequently Ri is controlled
by the biasing resistors only. They following equations are used to calculate rm.

………………….…….Equation 9.12

………….…..Equation 9.13

……………………………….Equation 9.14
 For a common-source (CS) amplifier, as shown in figure 9.6, equations 9.15
through 9.20 allow the calculation of amplifier characteristics. If there is any unbypassed
source resistance in the circuit, it must be added to rm in equation 9.17 and 9.18.

………………………….Equation 9.15
…………….………….….....Equation 9.16
…………………Equation 9.17

…………………..Equation 9.18

……………………….Equation 9.19
…………………...…..Equation 9.20

For a source follower (SF) amplifier, as shown in figure 9.7, equation 9.21
through 9.26 allow the calculation of amplifier characteristics.
………………………….Equation 9.21
…………….…….….....Equation 9.22
………………Equation 9.23

………………..Equation 9.24

……………………….Equation 9.25
…………………...…..Equation 9.26

9.4 Procedure
9.4.1: Determination of IDSS and VGS(off):
1. Connect the circuit of figure 9.1 (a) using 2N5457 JFET.
2. Measure the voltage across 1kΩ resistor and determine the measured IDSS by
dividing the voltage by 1kΩ. Record in table 9.1.
3. Connect the circuit of figure 9.1 (b) and adjust the VGG supply until the voltage
across 1kΩ resistor in the drain circuit is exactly half of the voltage measured in
step 2.
4. Measure and record the VGS voltage and determine VGS(off) by using equation 9.1.

Table 9.1 Measuring IDSS & VGS(off)

Figure 9.1 (a) Determined Figure 9.1 (b) Determine

Voltage across 1kΩ IDSS=V(1kΩ)/1kΩ VGS Voltage VGS(off)

9.4.2: Common-Source Amplifier Measurements:

 5. Connect the circuit of figure 9.6 using a 2N5457 JFET.
6. Check the dc conditions of your amplifier to be sure that it is operating correctly
before proceeding with the following ac measurements. The drain voltage should
be between 13 and 14V, while the source voltage should be between 6.1 and
9.6V.
7. Complete the table 9.2 with your measurements. Hint: Voc means output voltage
without load, and VL means the output load voltage. Using dual channel
oscilloscope, measure and sketch the both signals, and observe the phase shift
between input and output signals.
8. Remove the bypass capacitor on source resistor and repeat step7. Record your
results in table 9.3.

Table 9.2: Common-Source Amplifier Bypassed source resistor Measurements

Vg Voc VL

100mVp-p@ 1kHz

Table 9.3: Common-Source Amplifier Unbypassed source resistor Measurements

Vg Voc VL

100mVp-p@ 1kHz

Figure 9.6 Common-Source Amplifier Circuit

9.4.3: Source-Follower Amplifier Measurements:

9. Connect the circuit of figure 9.7 using a 2N5457 JFET.
10. Check the dc conditions of your amplifier to be sure that it is operating correctly
before proceeding with the following ac measurements. The source voltage
should be between 6.1 and 9.6V.
 11. Complete the table 9.4 with your measurements. Hint: Voc means output voltage
without load, and VL means the output load voltage. Using dual channel
oscilloscope, measure and sketch the both signals (Vi &Voc) and (Vi & VL),
observe the phase shift between input and output signals.

Table 9.4: Source-Follower Amplifier Measurements

Vg Voc VL

100mVp-p@ 1kHz

Figure 9.7 Source-Follower Amplifier Circuit

9.5 Questions

1. How does the voltage gain for a bypassed common-source amplifier compare to
that of a bypassed common-emitter amplifier?
2. How does the voltage gain for a source-follower amplifier compare to that of a
emitter-follower amplifier?
3. Assuming that ID=512µA, IDSS=1.0mA, and VGS(off)=-0.5V, calculate the voltage
gain for the circuit of common source amplifier that shown in figure 9.6.
4. Assuming that ID=800µA, IDSS=5.0mA, and VGS(off)=-6.0V, calculate the voltage
gain for the circuit of source-follower amplifier that shown in figure 9.7.
Experiment (10):

DIFFERENTIAL AMPLIFIER
10.1 Reference

Sections 12.2-12.4, Electronic Devices and Circuits, Differential Amplifier, Common

Mode Parameters, Practical Differential Amplifiers.

10.2 Objectives

1. To investigate the differential amplifier in the difference and common modes of

operation.
2. To determine the common mode rejection ratio (CMRR).

10.3 Discussion

Operational amplifiers are the most widely used electronic devices for linear
(non-digital) applications. The input stage to an op-amp is a differential amplifier. Most
differential amplifiers are constructed as integrated circuit, but to facilitate
experimentation, we will investigate a discrete version of the same circuit.

Differential amplifiers can be operated in either of two manners: the input signals
can be different, or the input signals can be identical. If the input signals are different, the
amplifier is said to be operating in its difference mode. This means that the output voltage
will be proportional to the difference in the two input signals. If the input signals are the
same, or the inputs are tied together, the amplifier is said to be operating in its common
mode.

Figure 10.1 shows a differential amplifier with small external emitter resistors
designed to compensate for any differences in the values of re of the two transistors.

The single and double-ended difference mode gains of the ideal differential
amplifier are:

The differential input resistance is:

Where:
rid: is the total ac resistance between the input terminals.
 Figure 10.1

The following equations apply to operation of the differential amplifier in its

common mode when the two input signals are equal in magnitude and phase:

The most important benefit of the differential amplifier in common mode

operation is the elimination of noise that is present at both inputs. Ideally, any noise
voltage that is present at both inputs is cancelled out by the phase inversion of the two
sides of the amplifier. The common mode rejection ratio (CMRR) is a ratio of signal gain
to noise gain that is, how well the amplifier amplifies the wanted signal and cancels the
unwanted noise. The single ended. CMRR is a ratio of the single-ended difference mode
voltage gain to the single-ended common-mode voltage gain. The double-ended CMRR
is a ratio of the double-ended difference mode voltage gain to the double-ended common-
mode voltage gain. Typically, the CMRR is extremely high (75 to 100dB is not
uncommon).

Where:
Ad: is the difference mode voltage gain
 Acm: is the common mode voltage gain

10.4 Procedure

1. To match two transistors, use DMM until two transistors are found with very similar
values of β.

2. Using the matched transistors for Q1, and Q2, connect the differential amplifier circuit
in figure 10.2. Make sure that the two 10kΩ resistors connected to the differential
amplifier's collectors are closely matched also (no more than 5% deviation). Also
measure the maximum resistance of the potentiometer (across its outer terminals).

Figure 10.2

3. With Vi1 and Vi2 set to 0V (grounded), connect a digital voltmeter between the outputs
VO1 and VO2 so it will read dc volts. Now adjust the 200Ω potentiometer until the
voltmeter reads 0Vdc. This procedure is called balancing the differential amplifier.

4. To determine the quiescent currents in the circuit, measure the dc voltage VRC across
each collector resistor and the voltage VRE across the emitter resistor of Q3.

5. Set Vi1 to 100mVp-p@1kHz and ground Vi2. Measure the ac voltage from the center
tap of the potentiometer to ground. Connect a dual-trace oscilloscope to observe and
measure the single-ended output voltages VO1 and VO2 with respect to ground. If the
oscilloscope has a difference mode setting, also measure the output difference voltage
(VO1-VO2). In each case note the phase relation with the input.

6. Set Vi2 to 100mVp-p@1kHz and ground Vi l. Repeat the measurements of procedure

step 5.

7. Using a single function generator set both Vi1 and Vi2 to 2Vp-p@1kHz. Repeat the
measurements of procedure step 5. The inputs may have to be increased above 2Vp-p if
the amplifier has an extremely small common mode voltage gain because the output
voltage may otherwise be too small to measure.

10.5 Questions

1. Using the dc voltage measurements made in procedure step 4, determine the collector
currents in each of the three transistors. Use these values to calculate the internal emitter
resistances re1 and re2 of Q1 and Q2, respectively.

2. Using the results of question 1, and the maximum resistance of the potentiometer
(which equals RE1+RE2), calculate the difference mode single-ended voltage gain with Vi1
set to 100mVp-p@1kHz and Vi2 set to 0V. Also calculate the differential voltage gain (or
double-ended voltage gain) using the same inputs. Compare these with the measured
values obtained in procedure step 5.

3. Calculate the value of Rid using the results of question 1 and the value for β.

4. using the results of procedure step 7, calculate the differential common mode gain and
calculate the CMRR in dB.

5. What is the purpose of the common emitter stage which has the differential amplifier
in its collector circuit?