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Digital IC Design Flow Overview

The document outlines the typical steps in a digital integrated circuit design flow including architecture design, RTL coding, verification planning, FPGA synthesis and placement & routing, ASIC synthesis, formal checking, netlist simulation, post-layout timing analysis, and post-layout simulation. Key data and checkpoints are listed for each stage of the flow.

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林冠宏
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530 views4 pages

Digital IC Design Flow Overview

The document outlines the typical steps in a digital integrated circuit design flow including architecture design, RTL coding, verification planning, FPGA synthesis and placement & routing, ASIC synthesis, formal checking, netlist simulation, post-layout timing analysis, and post-layout simulation. Key data and checkpoints are listed for each stage of the flow.

Uploaded by

林冠宏
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
  • SOI Digital IC Design Flow: Introduces the overall flow of digital IC design including stages like architecture design, RTL design, and their respective processes.
  • FPGA and Pre-Layout: Describes the FPGA synthesis and placement, followed by pre-layout tasks including formal verification and netlist simulation.
  • Design Flow Summary Table: Provides a tabulated summary of the design flow, including checkpoints and data locations for each major stage captured in the previous diagrams.
  • Post-Layout: Captures post-layout activities such as RC extraction, delay calculation, and simulation for final verification.

SOI Digital IC Design Flow

Digital IC Design Flow


Silicon Optronics, Inc
Digital IC Design Flow
Silicon Optronics, Inc

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Digital IC Design Flow
Silicon Optronics, Inc
Stage Flow Name Checkpoint Data Location
Architecture 1. Architecture Block diagram and timing diagram U:\Project\ProjectName\
Design review. DOC\DesignNote
RTL 2. RTL Coding RTL code review. /home/$USER/project/PRJName/
rtl
3. Verification Plan Verification plan review. U:\Project\ProjectName\
Verification
4. RTL Simulation RTL Simulation log check /home/$USER/project/PRJName/
sim/rtlsim/log
FPGA 5. FPGA Synthesis FPGA synthesis log review /home/$USER/project/PRJName/
fpga/synplify
6. FPGA P&R P&R log and timing report review. /home/$USER/project/PRJName/
fpga/xilinx
Pre-Layout 7. ASIC Synthesis ASIC synthesis log, timing and area /home/$USER/project/PRJName/
report review. syn/rpt
8. R2G Formal Check RTL vs. gate level logic equivalence /home/$USER/project/PRJName/
checking result. lec/r2g
9. Pre-Layout Netlist simulation log check. /home/$USER/project/PRJName/
Netlist Simulation sim/netsim/presim/log
Post-Layout 10. ASIC P&R Get netlist with clock trees from P&R /home/$USER/project/PRJName/
engineer. gate/post
11. RC Extraction & Get “Standard Parasitic Exchange /home/$USER/project/PRJName/
Delay Calculation Format” and “Standard Delay sta/sdf
Format” from P&R engineer.
12. G2G Formal Check Gate level vs. gate level logic /home/$USER/project/PRJName/
equivalence checking result. lec/g2g
13. Static Timing Timing report check. /home/$USER/project/PRJName/
Analysis sta/rpt
14. Post-Layout Netlist with RC delay simulation log /home/$USER/project/PRJName/
Netlist Simulation check. sim/netsim/postsim_bst/log
/home/$USER/project/PRJName/
sim/netsim/postsim_wst/log

Digital IC Design Flow


Silicon Optronics, Inc

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