Chapter 1

Thin film applications to microelectronic

technology

歐陽汎怡(Fan-Yi Ouyang )
 Outline
• Introduction
– Trend in electronic industry
• Reliability in first level interconnect (C4
solder bumps)
– Electromigration
– Thermomigration
– Stress migration
• Challenging reliability issues in 3D IC
• Summary
 Where are electronic devices used?
Everywhere!!!!!
• Desktop
• Notebook
• Server
• Embedded device
• Cell phone
• Workstation
• Smart TV
• Biomaterials
• Wireless adapters
• etc
 Demand for Electronic Device
High Density
Interconnection

High Speed Reduce EMI

Electro
Magnetic
Interference

Low Cost
Reduce Heat

Smaller Multi-function

Source : Lecture note of Prof. K. W. Paik at KAIST

Electronic materials and processing

Worldwide Electronic Equipment Sales :

Exceeding $US 1 Trillion

Courtesy of Prof. Zhong Chen, NTU, Singapore

The components of electronic device
X-section electronic device
• A: Key area of the chip and the focal point for increasing its
speed. Manufacturers are continually improving their designs,
making these devices smaller and more densely packed in
each square millimeter of silicon.
• B: physical or logical connection between two electronic
devices or networks. Usually consist of metal
• C: Method for interconnecting semiconductor devices, such as
IC chips and microelectromechanical systems (MEMS), to
external circuitry with solder bumps that have been deposited
onto the chip pads.
 First three levels of electronics packaging

MCM

Module or
First level packaging
Chip carrier)

Second level
packaging
PCB

mother board
Third level packaging
 Si--From Sand to circuit

Source: Intel PTD lab tour

documents

Silicon, the most abundant element on earth

except for oxygen, is used because it is a
natural semiconductor
 Si wafer
• Each die has two
major components:
– Transistor
– Backend
interconnect

Source: Intel PTD lab tour documents

 Transistor

• Today’s microprocessors use millions of

transistor connected together (integrated
circuits) to perform highly complex and
numerically intensive computation
• The transistor is a key area of the chip and the focal point for increasing its
speed. Manufacturers are continually improving their designs, making
these devices smaller and more densely packed in each square millimeter
of silicon.
• A transistor is a semiconductor device used
to amplify or switch electronic signals and electrical power. It is composed
of semiconductor material usually with at least three terminals for
connection to an external circuit. A voltage or current applied to one pair
of the transistor's terminals controls the current through another pair of
terminals. Because the controlled (output) power can be higher than the
controlling (input) power, a transistor can amplify a signal. Today, some
transistors are packaged individually, but many more are found embedded
in integrated circuits.
10-8 m - 70nm
Transistor -
smallest
device
(element)
inside an IC
• Achieving 70 nm
resolution is
Gate oxide equivalent to
drawing a coin
on the surface of
the earth from
the space
shuttle!!!
Courtesy of Prof. Zhong Chen, NTU, Singapore
 The first transistor-December 23, 1947

Walter Brattain & John Bardeen's pnp point-contact germanium transistor

operated as a speech amplifier with a power gain of 18 on December 23,
1947.
In January23 1948 William Shockley documented his idea for the Junction
Transistor.
1956 Nobel Prize for Physics to William Shockley, John Bardeen & Walter
Brattain for “Discovery of the Transistor Effect.”
 MOSFET Transistor
Integrated Circuit Device

Fig. 18.26, Callister &

Rethwisch 8e.

• MOSFET (metal oxide semiconductor field effect transistor)

• Integrated circuits - state of the art ca. 50 nm line width

– ~ 1,000,000,000 components on chip
– chips formed one layer at a time

16
Salicide process
 Moore’s law
• describes a long-term
trend in the history of
computing hardware
• The number of
transistors that can be
placed inexpensively on
an integrated circuit
has doubled
approximately every 18
months

Source: Intel PTD lab tour documents

 Intel transistor size trend

Source: Intel PTD lab tour documents

Innovation still continues…
https://www.extremetech.com/computing/162376-7nm-5nm-3nm-the-
new-materials-and-transistors-that-will-take-us-to-the-limits-of-moores-
law
 Backend interconnect

The VLSI of circuits is

achieved by
interconnecting all the
transistors together
using multilayer Al or
Cu thin film
interconnects

IBM J. of Research &

0.5 µm line width, and 0.5 µm line spacing
Development, July 1995
Þ 1 µm pitch
Þ 104 lines/cm, and each line is 1 cm long
Þ 100 m/cm2 in a single layer
Þ 1 km of interconnect per chip
 Interconnect
• Interconnects serve as the streets and
highways of the integrated circuit (IC),
connecting elements of the IC into a
functioning whole and to the outside world.
Interconnect levels (or metal layers) vary in
numbers depending on the complexity of the
device and are interconnected by etching
holes, called vias
Backend interconnect
Backend interconnect
 Backend interconnect: Cu
Cu/Oxide 8 Metal layers,
the alignment of 0.25 micron via structures: challenging !!

FIB cross-section Cross-sectional SEM after dielectric etch,

Free-standing Cu interconnects
• Interlayer vias: W
• Very thin adhesion and diffusion barrier layer: Ta, TiN

Institute of Microelectronics, Singapore

How to connect the on-chip VLSI
circuits to external circuits ?
 First three levels of electronics packaging

MCM

Module or
First level packaging
Chip carrier)

Second level
packaging
PCB

mother board
Third level packaging
 Four major functions of a package:
Signal Passage

Power Distribution

Heat Dissipation

Chip Protection
Trend of package technology
Single-chip Package Evolution Leading to Multichip Packaging
Smaller Size

Smaller Size, Weight

Higher Pin Count

SLIM: Single Level

Integrated Module

Year 1970s 1980s 1990s 2000-2010

Package types
 Packaging Evolution

1970s 1980s 1990s 2000 2005

Chip Connection Wire bond Wire bond Wire bond Flip Chip Low-cost Flip Chip
Package DIP PQFP P/C-BGA none
Package Assembly PHT SMT BGA-SMT none
Si Efficiency 2 7 10 25 >75

Area Array Peripheral

Chip up-side down Chip up-side up

 How Si connect package ??
Will need several thousands of I/O
Þ use an area array of tiny solder balls
Þ 50um diameter solder balls, 50um spacing
Þ 100 of them along a length of 1cm
Þ 10000 of balls on an area of 1 cm2
Wire bonding technology

Flip chip technology

The international technology roadmap for
semiconductor (ITRS): solder joint in flip
chip technology is an important subjects of
study concerning its yield in manufacturing
and its reliability in application since 1999
Packaging Level, Interconnection, and Technology
 Packaging Procedure with Leadframe

Wafer Leadframe
Die IC Chip
Saw Die
Attachment
Die Attachment

Connection Wire Encapsulation

Wire Encapsulation
Bonding

2nd Level SMT or PHT

Packaging Print Circuit Board
 Tape Automated Bonding (TAB/TCP) Procedure

Wafer Au bump
Die
Saw Die
Attachment

Lead coated with Sn

Inner lead
Au bumps bonding

Eutectic Au-Sn bonding

 The Evolution of Intel Microprocessor Packaging

Intel 8088 and 8086

microprocessors Intel i386™ microprocessor

Intel® Pentium® microprocessor

Chip-Connection Technology Status
日月光正在發展一個晶片
上面接一萬個銲錫接點!
 Flip chip technology
• C4 (controlled collapse chip
connect) 150um

• Under bump metallization

(UBM): tri-layer Cr/Cu/Au
– Cu: reaction with solder to form Via Si Chip
IMC
– Cr: glue layer (Cu to SiO2)
– Phase in Cu/Cr: improve adhesion
Eutectic SnPb or
– Au: surface passivation to prevent SnAgCu Solder
oxidation/corrosion Cr
• Surface finish Ni/Au Polymer Card
 Flip Chip Technology (C4)
Solder ball
Wafer IC

UBM & Die

Bumping Saw

Flip Chip
(C4) Joints IC
Reflow

Substrate
Underfill
Substrate
preparation
IC IC

BGA 2nd Level

Packaging SMT
BGA Solder Ball Print Circuit Board
 X-section electronic device

Source : Lecture note of Prof. K.N. Tu at UCLA

積體電路
的製作流程

Frontend

Backend

Packaging
Why do we seldom encounter
reliability failure in our
computers?
 This is because…….
Electronic industry has recognized the reliability
problem a long time ago

Þ Spent a lot of effort in conducting research into

understand the problem and failure mechanisms

Þ The mean time to failure (MTTF) of a computer

operating under certain accelerated test condition
has been measured

ÞThe lifetime of the computer in ordinary use can

be predicted!!!
 End of Moore’s law ??
• Limitation:
– Physically: can’t
keep shrinking
– Economically: profit
is not massive

Source: Intel website

• At the end of Moor’s law, the microelectronic

industry will not disappear.
• 2009 ITRS: Si technology still has room for progress in
the next 10 to 15 years.
 What will be in the future?
• As power delivery and bandwidth demands continue
to scale with silicon (Moore’s law) and system scaling,
packaging technology development that enables this
scaling will be critical

• If we shrink solder joints from 100um to 1um, it’s a

reduction of 10000 times in 2D density and may take
15 years to do so.

• Therefore, microelectronic industry is now shifting

emphasis to 3D IC, in which the merge of chip
technology and packaging technology is closer and
closer
 Slowing Moore’s Law Moore’s Law Limit
?
VLSI & (16 nm?)
104 ULSI
–Significantly : cost for chip
fabrication kk
CMOS
103 New IC Technologies
Computing Power (MIPS/K$)

LSI PC
Discrete
• Carbon Nanotubes
Transistors
• Low-K / High-K (Hf
Based)
• Strain Engineering
• DRAM → PRAM →
Vacuum Nanotube RAM
Tube • Flash: New
Technology S Curve
Architecture
• Binary Power
Technology’s
• NanoMEMS
Performance
Maturation
Relays • Soft Lithography…
New
Invention
10 -6 Explosive
Growth
Moore’s Law
Time/Effort

1940 1950 1960 1970 1980 1990 2000 2010 2020 2030 2040
Year

Courtesy: Dr. Yishao Lai, ASE.

3D IC 三維立體封裝

− Stacking
– Skyscraper
– Hamburger
– Parallel stacking
– Heterogeneous integration
Location : Malaysia Location : Taiwan Location : Dubai
Height : 452 M Height : 508 M Height : 705 M
Floors : 88 Floors : 101 Floors : 160
Built : 1998 Built : 2004 Built : 2008
Source: presentation material of Prof. K.N. Tu at UCLA
 3D-SIC TECHNOLOGY FOR FUTURE
DETECTOR
The integration of 3D technologies will enable performances, form factor, and
cost requirements of the next generation of electronic devices.
 Introduction: 3D IC integration

3D IC integration enables the improvement of

u IC performance,
u power consumption,
u system functionality
u form factor.

u 3D integration is an alternative solution to scaling issue in

CMOS circuits.

57
3D vertical wiring
Introduction: 3D IC integration

59
Interconnects in 3D IC
Si chip

1. Microbumps (~20 µm)

2. Through-Si-Via (TSV)
(~ 10-30 µm)
 Microbumps of 3D IC

Dramatic decrease in bump diameter (From 100 µm to 20 µm)

à Contact area decreases to 1/25! Solder volume drops to ~1/125!

(~100 µm in diameter ~ 20 µm

Solder
Microbump

C4/Flip-chip bump 61
 Development of Advanced packaging /
Heterogeneous integration

Ø Advanced packaging development (Moore’s Law

ü Heterogenous integration of chips in various
2.0 by TSMC) technical nodes / functions / materials / size

Ref: M.F. Chen, F.C. Chen, W.C. Chiou, D.C.H. Yu, System on Integrated Chips (SoIC(TM) for 3D Heterogeneous
Integration, 2019 IEEE 69th Electronic Components and Technology Conference (ECTC), 2019, pp. 594-599.

62
Ref: Y.H. Chen, C.A. Yang, C.C. Kuo, M.F. Chen, C.H. Tung, W.C. Chiou, D. Yu, Ultra High Density SoIC with Sub-micron Bond
Pitch, 2020 IEEE 70th Electronic Components and Technology Conference (ECTC), 2020, pp. 576-581.
 Development of Advanced packaging /
Heterogeneous integration

Ø Direct bonding / Hybrid bonding by TSMC’s SoIC ü Tremendous growth of Bump density by SoIC bonding
solution (Direct bonding / Hybrid bonding)

63
Ref: M.F. Chen, F.C. Chen, W.C. Chiou, D.C.H. Yu, System on Integrated Chips (SoIC(TM) for 3D Heterogeneous
Integration, 2019 IEEE 69th Electronic Components and Technology Conference (ECTC), 2019, pp. 594-599.
 Metal-to-Metal direct bonding techniques

Ø Surface activated bonding Ø Surface passivation bonding Ø Nanotwin bonding

Ref: T.H. Kim, M.M.R. Howlader, T. Itoh, T. Suga, Room temperature Cu–Cu Ref: Y. Huang, Y. Chien, R. Tzeng, K. Chen, Demonstration and Electrical Ref: C.-M. Liu, H.-W. Lin, Y.-S. Huang, Y.-C. Chu, C. Chen, D.-R. Lyu, K.-N. Chen, K.-N.
direct bonding using surface activated bonding method, Journal of Vacuum Performance of Cu–Cu Bonding at 150 °C With Pd Passivation, IEEE Transactions on Tu, Low-temperature direct copper-to-copper bonding enabled by creep on (111) surfaces of
Science & Technology A 21(2) (2003) 449-453. Electron Devices 62(8) (2015) 2587-2592. nanotwinned Cu, Scientific Reports 5(1) (2015) 9734.

Bonding
Methods Roughness (Rq) Bonding time Environment Remark
temperature
CMP /
Surface activated bonding 1.85 nm R.T. N.A. 10-8 Torr
Plasma activation
Surface passivation bonding 0.8 nm 150 ℃ 50 min 10-4 mbar Sputtering

Cu: 3.2 nm Cu:150 ~ 200 ℃ Cu: 10 ~ 60 min Cu: 10-3 Torr Cu: CMP
Nanotwin bonding
Ag: 11.3 nm Ag: 190 ~ 200 ℃ Ag: 3 ~ 5 min Ag: Atmosphere Ag: Sputtering

64
 Opportunity and challenge
• The consumer products market of 3D IC is very
large and it will grow for a long time.

• The 3D IC technology will have serious yield

and reliability problems to overcome before it
becomes mature and high volume production.

• New circuit design, new packaging technology,

and reliable materials will be required.