Thesis3 v11

A N U LT R A - L O W N O I S E , FA S T R E S P O N S E , H I G H A C C U R A C Y
A N D E F F I C I E N C Y P O W E R S U P P LY F O R E X P E R I M E N TA L
I N S T R U M E N TAT I O N P U R P O S E S
roel zwetsloot
November 4, 2020 – version 1.4

I would like to thank the following for their assistance in various
forms:
• Prof. Zian Qin for the opportunity, his patience, enthusiasm,

support and providing the environment where I could freely
work on my design as I saw fit.
• Both my parents for their motivating support even when grad-

uating seemed too frustrating to continue.
• Dr.eng. prof. P. Bauer and Ir. Bol for supervising the gradua-
tion process.
• Jelle Boele for the endless technical discussions and skill shar-
ing, keeping the mind sharp. That is, until the occasional beers
are involved.
• Jan Trompper for the insightful technical discussions and guid-

ance during the projects that have led to this project.
• Analog devices, Linear Technologies and Microchip for en-

abling the development of my practical skills on a student’s
budget through their free sampling programs.
"The master has failed more times than the beginner has even tried."
— Stephen McCranie
ABSTRACT
The purpose of this thesis is to evaluate a top-level topology for ultra-

accurate power supplies. Chapter 3 shows that precision power sup-
plies exist, but these are expensive and not stable on the long term.
The correction scheme proposed in chapter 2 brings the accuracy of
the best metrology systems to a high efficiency, low-noise power sup-
ply at a lower cost than either the multimeter capable of such accuracy
or the power supply capable of such low noise.
Whether this is possible hinges on the orthagonality of the top-

level design. Separation of functionality should allow each compo-
nent to have fewer or even only one selection criterium to perform its
function. This greatly reduces the cost and design complexity. To ver-
ify the theory behind top-level design, the critical parts are designed
with available components and tested. This should reveal any practi-
cal limitations which may render the approach useless in a realistic
scenario.
v
CONTENTS
1 introduction 1
2 orthogonal design strategy 3

2.1 Simple . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2 Global feedback . . . . . . . . . . . . . . . . . . . . . . . 3
2.3 Dynamic calibration . . . . . . . . . . . . . . . . . . . . 4
2.4 Thermal immunity . . . . . . . . . . . . . . . . . . . . . 5
2.5 Efficiency and speed . . . . . . . . . . . . . . . . . . . . 6
2.6 Separation in frequency . . . . . . . . . . . . . . . . . . 7
2.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 project orientation 11
3.1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2 Design goals . . . . . . . . . . . . . . . . . . . . . . . . . 12
4 power section 17
4.1 Goals and topology . . . . . . . . . . . . . . . . . . . . . 17
4.2 Circuit design . . . . . . . . . . . . . . . . . . . . . . . . 18
4.2.1 Pre-regulator . . . . . . . . . . . . . . . . . . . . 18
4.2.2 Linear regulator . . . . . . . . . . . . . . . . . . . 19
4.2.3 Low-pass filter . . . . . . . . . . . . . . . . . . . 21
4.2.4 Sinking capability . . . . . . . . . . . . . . . . . . 22
4.2.5 Headroom sensing feedback . . . . . . . . . . . 23
4.3 Test Results . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.3.1 Efficiency . . . . . . . . . . . . . . . . . . . . . . 24
4.3.2 Ripple rejection . . . . . . . . . . . . . . . . . . . 25
4.3.3 Settling time . . . . . . . . . . . . . . . . . . . . . 26
4.3.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . 27
5 forward control 29
5.1 Goals and topology . . . . . . . . . . . . . . . . . . . . . 29
5.2 Setpoint DACs . . . . . . . . . . . . . . . . . . . . . . . . 30
5.3 Voltage mode controller . . . . . . . . . . . . . . . . . . 32
5.3.1 Ground forcing . . . . . . . . . . . . . . . . . . . 32
5.3.2 Detailed design . . . . . . . . . . . . . . . . . . . 32
5.4 Current mode controller . . . . . . . . . . . . . . . . . . 33
5.4.1 Scaling . . . . . . . . . . . . . . . . . . . . . . . . 34
5.4.2 Noise coupling . . . . . . . . . . . . . . . . . . . 36
5.5 Test Results . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.5.1 Controller mode switchover, peaking and stability 37
5.5.2 Step response . . . . . . . . . . . . . . . . . . . . 37
5.5.3 Load rejection . . . . . . . . . . . . . . . . . . . . 38
5.5.4 Noise . . . . . . . . . . . . . . . . . . . . . . . . . 39
vii
viii contents
5.5.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . 41
6 correction for accuracy 43

6.1 The ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.2 The References . . . . . . . . . . . . . . . . . . . . . . . 44
6.2.1 Practical notes . . . . . . . . . . . . . . . . . . . . 45
6.3 Voltage sense interface . . . . . . . . . . . . . . . . . . . 46
6.3.1 Multiplexer . . . . . . . . . . . . . . . . . . . . . 46
6.3.2 Funnel amplifier . . . . . . . . . . . . . . . . . . 47
6.4 Current sense interface . . . . . . . . . . . . . . . . . . . 51
6.5 Correction . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6.6 Test Results . . . . . . . . . . . . . . . . . . . . . . . . . 53
6.6.1 Data rate . . . . . . . . . . . . . . . . . . . . . . . 53
6.6.2 CMRR and ISI . . . . . . . . . . . . . . . . . . . . 54
6.6.3 Linearity . . . . . . . . . . . . . . . . . . . . . . . 54
6.6.4 Reference . . . . . . . . . . . . . . . . . . . . . . 54
6.6.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . 55
7 full system analysis 57

7.1 Topology Phase . . . . . . . . . . . . . . . . . . . . . . . 57
7.2 Design phase . . . . . . . . . . . . . . . . . . . . . . . . 57
7.3 Prototype phase . . . . . . . . . . . . . . . . . . . . . . . 58
7.4 Conclusion & Recommendations . . . . . . . . . . . . . 60
a system hardware 61
a.1 Layers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
a.2 Partitioning . . . . . . . . . . . . . . . . . . . . . . . . . 61
a.3 digital . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
a.3.1 Interface . . . . . . . . . . . . . . . . . . . . . . . 63
b test hardware 65
b.1 Ground loop precautions . . . . . . . . . . . . . . . . . 66
b.2 RMS measurement . . . . . . . . . . . . . . . . . . . . . 66
bibliography 67
LIST OF FIGURES
Figure 1 Simplest implementation of output control. . . 3

Figure 2 Basic stabilization though digital feedback. . . 4
Figure 3 Advanced digital feedback with zero and gain
calibration. . . . . . . . . . . . . . . . . . . . . . 4
Figure 4 Error correction sequence. . . . . . . . . . . . . 5
Figure 5 Thermally stabilized implementation of figure 3. 6
Figure 6 Figure 5 modified for higher efficiency and faster
control. . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 7 Frequency ranges. . . . . . . . . . . . . . . . . . 7
Figure 8 Low noise power supply comparison taken from
Keysight B2962A specification sheet [7] . . . . 12
Figure 9 Power conversion subcircuit. . . . . . . . . . . . 17
Figure 10 Transconductor device, a BJT, in follower con-
figuration. . . . . . . . . . . . . . . . . . . . . . 20
Figure 11 The inserted low-pass filter. Co is the output
capacitor of the preceding regulator or DC/DC
converter, Lf , Cf and Rd form the damped filter. 22
Figure 12 Current sinking circuit. . . . . . . . . . . . . . . 23
Figure 13 Headroom sensing amplifier. . . . . . . . . . . 23
Figure 14 Power delivery efficiency. . . . . . . . . . . . . 24
Figure 15 Ripple attenuation of 1st LPF stage. . . . . . . 25
Figure 16 1V/15V step response. t = 0 Denominates DAC
data latching. . . . . . . . . . . . . . . . . . . . . 26
Figure 17 Controller circuit. . . . . . . . . . . . . . . . . . 29
Figure 18 Error waveforms due to DAC setpoint correction. 31
Figure 19 Voltage control section. . . . . . . . . . . . . . . 33
Rs
Figure 20 Setpoint attenuation with A = 4.096V < 1. . . . 35
Figure 21 Current sense amplification with G = 4.096V Rs > 1. 35
Figure 22 Current control section. . . . . . . . . . . . . . . 36
Figure 23 Voltage step response with current-limited slew-
ing due to capacitive load. . . . . . . . . . . . . 38
Figure 24 1V rising step response with small load (220Ω) 38
Figure 25 1V falling step response with small load (220Ω) 39
Figure 26 Loading rejection with the system operating at
2V, 500mA responding to a current load de-
crease of 200mA lasting 30ms. . . . . . . . . . . 39
Figure 27 Short-term noise measuring both a short and
Ṽout operating at 4V/100mA. . . . . . . . . . . 40
Figure 28 Scaling down the main reference for the ADC.
Rf = Ru ||Rd 1. . . . . . . . . . . . . . . . . . . . . 45
ix
x List of Figures
Figure 29 Multiplexer and funnel amplifier detailed con-

nection. . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 30 Funnel amplifier circuit. Guard rings are shown
with dashed grey lines. . . . . . . . . . . . . . . 49
Figure 31 The straight-forward connection of Rs to the
ADC. . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 32 Division of system cycles. . . . . . . . . . . . . 52
Figure 33 PCB cross-section view of the reference area. . 62
Figure 34 PCB top view with partitioning marked. Fig-
ure 35 shows fished result. . . . . . . . . . . . . 63
Figure 35 Completed test assembly with shield covers re-
moved and additional SMA test connectors mounted. 64
Figure 36 Low noise oscilloscope preamplifier schematic. 65
Figure 37 LNA with cover removed (left) and battery as-
sembly of the RMS meter (right) as present on
both units. . . . . . . . . . . . . . . . . . . . . . 66
L I S T O F TA B L E S
Table 1 Various power supplies on the market. . . . . . 15

Table 2 Design specifications. . . . . . . . . . . . . . . . 16
Table 3 Small-signal pass element comparison at 5V,
1A output with 1V headroom. . . . . . . . . . . 21
xi
ACRONYMS
ADC Analog to Digital Converter
BJT Bipolar Junction Transistor
CMRR Common Mode Rejection Ratio
DAC Digital to Analog Converter
DNL Differential Non-Linearity
INL Integral Non-Linearity
LDO Low DropOut regulator
LSB Least Significant Bit (internal digital variable)
LSD Least Significant Digit (Externally controllable variable)
PCB Printed Circuit Board
POL Point of Load
PSRR Power Supply Rejection Ratio
SMPS SwitchMode Power Supply
TUE Total Uncompensated Error
xii
INTRODUCTION
1
This work continues on a development done during an internship at
the now bankrupt Mapper Lithography B.V. This internship focused
on developing an ultra stable and accurate bipolar current source in
order to control the actuators and deflectors of electron beams. This
development was necessary, since off-the-shelf solutions were too ex-
pensive and insufficient. As the design proceeded several ideas were
left untested; such as embedding an heater in the PCB to control the
temperature of critical components, full-system dynamic calibration,
an anti-saturation system improving transient behaviour, digital drift
compensation and several others. When grouped together these ideas
give shape to an overall design strategy which may be applied in de-
signing a more complete and commercially viable power supply unit.
A fully functional unit poses many more design challenges than the
original project, but promises to be a viable market product.
To verify the feasibility of this higher level strategy not only the
theory itself must be evaluated, but also whether it allows for im-
proved performance with practical components. Practical obstacles to
the success of the design strategy are best discovered by performing
an initial development iteration; such is the goal of this document.
• The theory behind the design approach will be investigated.
• Design goals are chosen to provide a market-viable result.
• Modules critical to the operation of the design will be investi-

gated from a designer’s point of view in order to expose practi-
cal limitations.
• The result of these designs will be subjected to tests. These tests

may further expose unforeseen physical limits, flaws and design
difficulties.
• With the information from previous steps the feasibility and

usefulness of the design approach may be evaluated.
1
O R T H O G O N A L D E S I G N S T R AT E G Y
2
2.1 simple
Designing a small circuit that is best at performing all tasks simul-

taneously is difficult. A low noise, high speed system is especially
difficult to make accurate. Figure 1 shows a power delivery system
where all components in the chain need to be optimized for noise,
speed, linearity, short and long term accuracy, efficiency and output
impedance. Since no global feedback is present the individual errors
compound and calibration only compensates for initial accuracy. Wire
losses between the buffer and the point of load (POL) are also left un-
compensated.
Figure 1: Simplest implementation of output control.
2.2 global feedback
Separating this functionality across other devices is helpful. Figure

2 separates accuracy from speed and noise. Initial accuracy of the
forward chain is no longer important, since this task now falls to
the feedback paths. The components of the feedback paths now only
need to be designed for high accuracy and linearity. Since it is now
also much easier to correct the system, drift after initial calibration
is much less of an issue. The DAC and output buffer may now be
optimized for low noise , speed and efficiency so partial separation is
achieved.
An additional user-accessible load-sense feedback channel is added.

This allows the user to take feedback directly from the POL, allowing
for compensation of wire losses when this is desired. POL accuracy
is now no longer dependent on external cabling. However the errors
of the ADC and feedback block still compound, and now there are
two feedback channels. This comes at twice the cost and gives mis-
match in DC force/sense performance as channel errors will not be
identical.
3
4 orthogonal design strategy
Figure 2: Basic stabilization though digital feedback.
2.3 dynamic calibration
Figure 3: Advanced digital feedback with zero and gain calibration.
In the schematic of figure 3 the same channel is now used for both
force and POL voltage measurement. The circuit used to implement
this also allows for easy continuous correction of the output voltage.
This continuous process is shown in figure 4. The system response
(black line) is corrected to align with the calibration points (circles) in
two steps:
• Step 1: The input is connected to zero, and the measured output

code Kos is stored for offset correction. It will be subtracted
from subsequent measurements.
• Step 2:The input is connected to the reference with a known

value. A correction multiplier Kgain is calculated and stored.
This multiplier corrects the gain difference, or the angle between
the black and dashed line in the gain corrected panel of figure
4.
2.4 thermal immunity 5
• Step 3: When measurements to the output or POL are performed

the transformation Vout = Kgain · [ADC Code − Kos ] is applied
to subsequent measurements.
Original Offset corrected Gain corrected

12 12 12
10 10 10
8 8 8
Output code
6 6 6
4 4 4
2 2 2
0 0 0
0 5 10 0 5 10 0 5 10
Input code Input code Input code
Figure 4: Error correction sequence.
The parameters used for correction may be internally filtered over

multiple cycles to achieve a smooth correction response. Now the
ADC and the feedback block only needs to be optimized for linearity,
the reference for stability, and the DAC/buffer for lowest noise and
speed. The multiplexer serves the dual purpose of eliminating the
second feedback channel of figure 2 and applying known parameters.
The calibration scheme of figure 3 maintains it setpoint well if the

reference voltage is stable. Unfortunately even the reference with the
highest temperature immunity is dependent on other components
whose drift may dominate over that of the reference itself[21].
The system we have previously described can zero-out tempera-

ture errors in other components than the reference as long as the
interfering frequency remains below the calibration frequency. Fre-
quencies above this threshold appear as noise at the output. By insu-
lating the circuit from its environment we can drastically reduce fast
temperature variations.
2.4 thermal immunity
Shielding and repeatable reference temperatures are achieved by

adding thermal stabilization inside the shield as is depicted in figure
5. While the LTZ1000 has a thermal stabilization system of its own,
this requires external components of exceptional quality and corre-
sponding price to be effective. Including these inside a thermally sta-
bilized area helps to decrease overall drift, increases the efficiency of
the heater, and if the shield is made of metal it also stops EMI. This
eases the price and cost of these additional components. Since con-
trollable cooling is much harder to achieve compared to heating, the
temperature setpoint should be chosen above maximum ambient tem-
perature. This system is experimental and may not be cost-effective.
Figure 5: Thermally stabilized implementation of figure 3.
2.5 efficiency and speed
The output section is now shown as a simple buffer amplifier. This

simplified implementation limits the response time of the system as
the digital control loop will not be able to compensate medium to
high frequency errors as fast as an analog one. Additionally, if this
buffer is implemented as a traditional LDO it will dissipate signifi-
cant power. If this heat couples into the system it will cause dynamic
temperature gradients when the load changes. This in turn causes
drift errors as thermocouple voltages at component contacts change.
Modern regulators can achieve outstanding low noise levels and

PSRR at the expense of their power handling capability. For optimal
performance the regulator must be given the minimal voltage needed
for full performance and not more. Therefore a headroom controlling
converter is added to the system in figure 6. This pre-regulation cir-
cuitry may be physically far from the regulator itself to reduce its
thermal influence on the area of the precision circuit.
If the PSRR of the regulator is insufficient, additional filtering may

be applied before or after the regulator. If this LPF (low-pass filter) is
placed after the regulator it will not only reduce the high frequency
noise of the DC/DC converter but also of the LDO. Filtering between
the DC/DC converter and the LDO improves the spatial separation
of low and high noise signals. As well as reducing the attenuation
needed per filter segment. When both are applied, each filter may be
of a much more simple design.
The analog controller still needs to account for fast changes in

output loading and, if needed, fast constant current mode (CC) to
2.6 separation in frequency 7
constant voltage mode (CV) switch-over and vice versa. Actions like
these are best left to analog circuitry which leads to introducing a
separate controller that is no longer integrated in the regulator. This
simultaneously increases low-power PSRR of the compound circuit,
as much higher open-loop gain is achieved. Since this controller may
be susceptible to EMI it is best to have it shielded.
Figure 6: Figure 5 modified for higher efficiency and faster control.
2.6 separation in frequency
The proposed design approach has resulted in effective separation of

functionality. Most aspects of functionality change with frequency, so
as a result division into frequency ranges can be made as depicted in
figure 7.
Figure 7: Frequency ranges.
• DC to f1 , the lower or digital is the range where the digital feed-

back loop eliminates drift. It is the domain of precision electron-
ics. Due to the digital system the theoretical output impedance
should be negligible in this low frequency region. Applicable

techniques are drift elimination and dynamic calibration.
• f1 to f2 , the lower active or analog controller range is where

the analog controller ensures that fast load changes are rejected
until the digital system can catch up. Both current and voltage
are controlled. This analog circuit can only reduce the output
impedance at the terminals of the supply. The response time
of CC/CV circuitry must also be in this range, since we want
the fastest response time available. Design is mostly centered
around fast response, low noise systems.
• f2 to f3 , the upper active or open-loop range. The controller

has reduced influence over the behaviour of the regulator as
frequency increases, which acts as a voltage source. Therefore
the regulator is mostly responsible for output noise. Constant-
current mode current noise is dependent on load impedance.
• f3 and above, the high frequency range. This is where semicon-

ductor systems are too slow to be effective. System performance
depends mostly on passive elements.
2.7 conclusion
Several other observations can be made with respect to separation:
• The headroom DC/DC converter gives maximized efficiency

and frees the LDO from power handling.
• A high switching frequency used with additional post-filtering

eases the PSRR requirements of the regulator. If just one filter
stage is sufficient, it should be placed after the regulator.
• The analog controller frees the regulator from medium-frequency

accuracy.
• The analog controller frees the digital controller and mixed sig-
nal circuits from fast CC/CV switch-over action.
• The regulator and LPF provide high PSRR, low noise and out-
put impedance at high frequencies.
• The feedback system separates the output control (DC/DC, reg-

ulator, DAC, controller) from DC accuracy caused by wire losses
and component tolerance.
• Dynamic correction separates the feedback system from long-

term errors, component tolerance and offset.
• The embedded heater rejects ambient temperature changes to

stability.
2.7 conclusion 9
Now that we have separate subcircuits, we can design and test them
separately to meet the part of the design goals they are responsible
for. If there are no critical oversights in design methodology, the test
result of the whole system should be equal to the core aspects of each
separate part.
P R O J E C T O R I E N TAT I O N
3
3.1 applications
The level of performance proposed for this project is not out of reach.
There are multimeters with 6.5 or even 8.5 digits as well as power
supplies capable of delivering low noise power, adjustable in very
small steps. Yet the value of the proposed system has shown itself
during the development and testing stages of several other projects
for the following reasons:
• Price: The power supply and multimeters needed to achieve

the same power quality each cost several tens of thousands of
dollars; if both voltage and currents need to be monitored, two
multimeters are often needed.
• Fine control: A controllable power supply with sufficiently small

least significant digit (LSD) and good high-frequency noise per-
formance is needed. These are uncommon and expensive.
• Cost Efficiency: Most of the functionality of each multimeter is

left unused, as well as the additional features usually present in
high-end power supplies.
• Size: The two or three stand-alone systems take significant space,

require proper cabling and a computer to perform controlling
action resulting in a cumbersome system.
• Readiness: The computer processing the data from the multi-

meters and adjusting needs to be set up by the operators. This
takes significant effort, even more so if the operator is less fa-
miliar with the operating system(s). Therefore the compound
system is not easily set up for any form of quick testing.
• True low-noise: The power supply that can deliver the targeted
noise level only does so with a significant passive band-limiting
filter. This reduces noise at the cost of output impedance, tran-
sient response and maximum output power. Therefore this sup-
ply can not be considered self-contained for the application even
when accuracy is left out of the consideration.
The amount of effort and funds needed to set up such a system is

out of reach for most smaller laboratories. Applications of this sup-
ply include low-noise analog engineering, RF engineering, analog IC
design, device characterization and metrology. An inexpensive and
11
12 project orientation
h!
Figure 8: Low noise power supply comparison taken from Keysight B2962A
specification sheet [7]
self-contained power supply will make precision engineering much

more accessible to the laboratories seeking to do so, and save valuable
time for the tasked engineer.
3.2 design goals
The result of this research must offer a competitive position compared

to available units in these fields. Therefore it must offer improvements
in a combination of accuracy, efficiency, ease of use and price. Flex-
ibility in range and additional features may be sacrificed to reduce
cost, therefore keeping it accessible to a wider range of end users. Ta-
ble 1 shows several representative power supplies currently available
on the market to which this power supply may be compared once
completed.
The Keysight B2962A is the only power supply capable of achiev-

ing the target noise level Ṽ 1 . It is also a key selling point of the unit,
see figure 8. This figure corresponds well to power supplies listed in
table 1. However, the case analysis concerning accuracy from chapter
3.1 applies to the B2962A as it’s drift V̇ 2 leaves room for improvement.
We may use this device as a source of inspiration; its performance is
excellent although the price is suspected to come from its astound-
ing flexibility. It must be noted that this low noise level comes at the
cost of settling time as the noise level is only achieved using a pas-
sive low-pass filter; this both increases its output impedance to 50Ω
1 Noise quantities are capped by ’~’, such as current noise Ĩ.

2 Error quantities are capped by ’·’, such as current error İ.
3.2 design goals 13
and reduces its ability to produce fast waveforms, react speedily to

changes in output setting or changes in output load. Therefore the im-
proved noise performance comes at significant cost. Proposed higher
level design targets are as follows:
• Noise should be in the same order of magnitude as the best unit

available on the market without the need of additional external
filtering as a high output impedance must be avoided. The com-
mon test bandwidth of 10Hz - 20MHz will also be used. Due
to the nature of the design strategy, the output noise as percent-
age of the full-scale range (FSR) output voltage is limited by the
ADC as shown in equation 12.
• Accuracy must be a key design aspect. Its accuracy should be

equal to its external control step size VLSD or ILSD .
• Force/sense ports should be present to achieve maximum point-

of-load accuracy.
• A hybrid power structure will be used as it was proven suc-

cessful in earlier work. VFSR was limited by component choice
in that design. While the this work has an improved output
stage able to handle higher voltages, increasing output voltage
is likely of little use in most applicable situations. For most use
cases VFSR = 15V appears sufficient.
• The full scale output current IFSR will be arbitrarily set at 1A.
Higher output currents can be obtained by using power stages
in parallel, either hard-wired or with multiple power supplies.
IFSR is twice that of the nearest competitor capable of having a
similar İ.
• The design does not need to be bipolar or wide-range. This

would greatly increase engineering effort and significantly in-
crease cost.
• Resolution should be competitive but not at an excessive price.

Increasing resolution beyond its accuracy only has value if it
comes at little cost.
• The ability to program medium speed waveforms (>200Hz) with

any accuracy would add too much complexity and significantly
increase cost. This does not exclude settling time and load-step
rejection from being competitive, but allows for inaccuracy dur-
ing set-point transients as well as a lower correction speed.
• The final unit should allow digital programming via a computer

link although this is not within the scope of this project yet.
• Size and weight should be minimized, although it is of lower

priority than all other restraints.
• The final target price should below $1000. To cover unforeseen

issues and the additional costs of possible mass-production, the
initial goal should be $500.
This results in the numerical requirements as shown in table 2.

korad kd3005d ea-ps 8032-10 rigol dp832a Keysight B2962A
no noise filter with noise filter
Target low cost, gen. purpose power/efficiency balanced performance flexibility/accuracy

Pout 150W 320W 90W 31.5W 10.5W
FSR 30V/5A 32V/10A 30V/3A ±21V/±1.5A ±21V/±0.5A
Resolution 30ppm 280ppm 33ppm 1ppm
Accuracy 5000ppm 2100ppm 2000ppm V̇ = 400ppm, İ = 1800ppm
67ppm/2mV 320ppm/10mV 12ppm/350µV 17ppm/350µV 0.5ppm/10µV
RMS Noise 600ppm/3mA 700ppm/7mA 670ppm/2mA Unknown 20ppm/10µA
20Hz - 20MHz < 300kHz 20Hz - 20MHz 10Hz - 20MHz
Settling time < 100ms < 30ms 15µs 110µs 140ms
Force/Sense No No No Yes
Digital control No Partial Yes Yes
Power system Linear Switching Linear Hybrid
Volume 44.6dm3 6.1dm3 15.7dm3 22.5dm3 22.8dm3
Weight 4.8kg 3.8kg 10.kg 6.4kg 6.7kg
Price w.o. tax $60 $700 $730 $10030 $12200
Table 1: Various power supplies on the market.

3.2 design goals
15
specification normalized
VFSR 15V 1
IFSR 1A 1
VLSD 100µV 6.7ppm
ILSD 10µA 10ppm
Ṽrms < 10µV 6ppm
Ĩrms < 5µA 5ppm
V̇ 100µV 6.7ppm
İ 250µA 250ppm
τ15mV 1ms -
Table 2: Design specifications.

POWER SECTION
4
4.1 goals and topology
The subcircuit of this chapter is shown in figure 9. Its purpose can be

described as follows.
Figure 9: Power conversion subcircuit.
• It should accept external power (Vin ) and convert it to a voltage

determined by an external reference (Vset ) in the range of 0 to
at least 15V and supply sufficient current at this voltage, 1A as
defined in table 2.
• The noise contribution of this subsystem should be minimized

with respect to the full system. Since this circuit is enclosed
within a feedback loop any < f2 noise is easily rejected. The f2
to f3 noise of the regulator may not contribute more than one
third of the total output noise, the other thirds being reserved
for the controller and the correction scheme.
• The circuit should reject voltage changes of the input power

source. Its PSRR should be so high that its output noise is not
affected by input voltage change.
• Since the circuit is enclosed within the analog feedback loop

its reference tracking speed should exceed well beyond f2 to
ensure a stable system.
• Because the analog system deals with only small changes in out-
put voltage, the headroom regulating DC/DC converter does
not need to be as fast and the settling time to design for is equal
to τ2 (= f12 ).
17
18 power section
4.2 circuit design
4.2.1 Pre-regulator
While the circuit in the application example of LT3045 [3] was taken
as a starting point, the assumption to use an SMPS pre-regulator may
not seem an obvious one.
The requirement to settle within 1ms disqualifies controlled line-

rectified topologies; the response time of such a system depends on
the bulk capacitance needed to smoothen its output. If the bulk ca-
pacitance is sufficiently small to be charged fast enough to meet
the settling requirement, the line frequency ripple (50/60Hz, t =
20ms/16.7ms) is no longer rejected. This is aside from the bulky and
heavy components required for line rectification and filtering.
An argument can be made to apply another linear regulator op-

erating as a cascode. This first linear regulator stage then offers a
significant reduction in ripple and noise. Because it need not be as
fast as the final LDO it may be physically far removed from the rest
of the circuit to reduce its significant heat signature on the system.
It is a simple solution and it works, but it is also an inelegant and
inefficient solution requiring a lot of space.
This leaves the DC/DC converter to be investigated. Such a con-

verter may have a much faster control response and it is also very
efficient. The topology choice and operating frequency determine the
viability of this solution. As the switching frequency is lowered its
properties come closer to the line rectified topology, and with the pre-
vious conclusions in mind the highest possible switching frequency
appears attractive. However the fast response, the small, light and
cheap passive components come at the cost of ripple at higher fre-
quencies and EMI. This is disadvantageous for the following regula-
tor stage. Semiconductor device PSRR drops as frequency increases,
but for passive filtering the opposite holds true. By inserting such
a passive low-pass filter (LPF) the system PSRR is greatly improved
and we can choose the highest viable switching frequency. This is
orthogonality on a smaller scale.
Only the SMPS topology remains to be chosen. If the regulator is

always operated with 1V of regulation headroom, we may conclude
that it needs 1 to 16V at its input to operate across the desired range.
Theoretically all topologies can be applied with various levels of suc-
cess; buck, boost, inverting, flyback, forward etc. Since designing con-
trollable isolated AC/DC converters is neither easy nor a part of this
4.2 circuit design 19
thesis1 , the discussion is limited to low-voltage un-isolated DC/DC

converters. Of these the buck converter offers the lowest ripple due to
it being the only converter where the inductor current continuously
flows into the filter capacitance. Due to the same property it also of-
fers the lowest peak inductor current. With these advantages and sev-
eral other minor advantages it becomes easy to see why the choice
for an high frequency buck converter remains valid if the LPF does
its work. While many converter ICs sport high switching frequencies,
only few have a very low minimum on-time. Under light load or at
large conversion ratios the minimum on-time is reached; when this
happens the duty cycle can only be reduced further by reducing oper-
ating frequency. This frequency reduction or pulse skipping reduces
the effectiveness of the LPF. LT8608 was chosen due to its very low
minimum on-time of 35ns [5]; this allows the converter to operate at
its nominal frequency even at very light loads.
The input voltage sets the operating area where frequency reduc-
tion occurs. Only a few off-the-shelf AC/DC converter output volt-
ages are available in the useable range:
• 6 16V is not possible due to the Vin > Vout requirement of the
headroom regulating buck converter topology.
• 18V would appear ideal, except that the maximum duty cycle
becomes very large. Most converters have a minimum off-time.
Such a low input voltage also reduces the headroom avaiblable
to cope with copper losses, and the forward controller op-amps
require more headroom voltage[14] to operate than available
with an 18V supply.
• 24V sets the voltage below which frequency foldback occurs
from 2MHz nominal at 1.7V (see eq. 1) or 35mA[5].
• > 36V is feasible, yet the resulting operating frequency and effi-
ciency is degraded with respect to 24V.
D Vout,min 1
fmin = = = = 1MHz (1)
ton,min Vin,max · ton,min 24V · 35ns
An off-the-shelf 24V supply allows for the best set of operational
parameters. Such modules are widely and cheaply available.
4.2.2 Linear regulator
The IC that sparked the design approach form this project is the
LT3045 [3]. Unaware that components existed that were capable of
1 Off-the shelf converters offer many advantages. No development time, certification
cost and their proven designs at very low unit costs make them an attractive solution
to obtain a raw power supply, ’Vin ’.
20 power section
such feats, attempts were already made earlier to reach the perfor-
mance level required with discrete components or composite circuits.
Any transconductance device could be used as they generally obey
the low-frequency small-signal equation Ids = Vgs · yfs + Vds · yos .
Vcc Vcc
IN
IN
Rload Rload
A B
Figure 10: Transconductor device, a BJT, in follower configuration.
Application as a emitter follower2 as shown in figure 10 is further

detailed in [16, p. 468]. In short, high forward conductance (yfs ) and
negligible output conductance (yos ) are desired. With larger yfs the
gain comes closer to unity and with smaller yos the supply rejec-
tion approaches infinity. Deficiency in yos can be overcome through
greater control action, which is only applied in figure 10b. Since the
LDO is inside the feedback loop its < f2 noise is almost entirely coun-
tered by the controller. However, for > f2 , where the switching fre-
quency resides, the controller has almost no influence. This makes
PSRR and noise performance at high frequencies the key parameter.
Based on such observations we may compare the PSRR of discrete

devices, composite circuits and the LT3045 as well as another com-
parable LDO as described in table 3. These specifications based on
datasheet values and calculations shows the clear advantage of inte-
grated circuits over discrete components. While at first the LT3045
seems the ideal choice, its issue is its limited output voltage. Any
copper losses within the complete system as well as the voltage drop
needed to sense output current will render the LT3045 unable to
meet the 15V output requirement. While the PSRR and noise of the
TPS7A4701 are slightly inferior, the deficiency is small enough to be
overcome by passive components.
2 Or source/cathode follower, common drain/collector/anode amplifier depending

on the active element and naming preference.
BCP56 Composite LT3045 TPSA7A4701

3
Gain 0.99 1 1 1
PSRR 1kHz 6dB 106dB 110dB 75dB
PSRR 6dB 50dB 80dB 65dB
1MHz
Ṽ ? 1.5µVRMS 1.8µVRMS 4µVRMS
Iout 1A 1A 500mA 1.2A

Vmax 80V 28V 15V 34V
Cost $0.1 $3.60 $3.10 $3.01
Table 3: Small-signal pass element comparison at 5V, 1A output with 1V

headroom.
4.2.3 Low-pass filter
The ripple at the output of the DC/DC converter is stated as Ṽraw =

10mV [5], but measurements in early proof of concept designs have
shown 20mV worst case. This ripple is attenuated with at least 50dB
by the LDO, yet this leaves at least 63µVpp ≈ 22.4µVRMS of output
ripple. This amount is unacceptable but can be further attenuated by
an LPF. The design considerations for the LPF are as follows:
• The filter must be designed for ’low-low’ component corners; all

capacitors and inductors must be used at their minimum value
of their tolerance band. An additional 10dB headroom is added
to account for design errors, PCB flaws, forgotten parasitic ef-
fects etc.
• Due to DC saturation and biasing in inductors and capacitors,

the filter must be designed operating at 1A and 16V applied
respectively.
• The filter itself may not resonate; therefore the design target
is ζ > 0.707. Allowing a small amount of power loss greatly
improves cost-effectiveness and damping.
• The filter may be placed before and/or after instead of before

the regulator, as long as full system stability can be guaranteed.
The LPF then also sets f3 , attenuating not only SMPS noise but
also controller and regulator noise for higher frequencies.
• LPF must attenuate the residual ripple enough for the remain-
ing noise to be inconsequential with respect to other noise con-
tributions; there residual ripple may therefore not exceed 3.3µVRMS .
22 power section
12.5µV
G1MHz = 20Log[ ] + 10dB = 26.6dB (2)
3.3µV
The circuit in figure 11 is based on basic calculations and refined to

include parasitcs in LTspice, giving the following results:





−31.5dB 1MHz, datasheet minimum values
Glpf = −34.5dB 1MHz, nominal values (3)




−46dB, 2MHz, nominal values
Rd Lf
68m 68nH
IN OUT
Co
Cf
2x10F
Figure 11: The inserted low-pass filter. Co is the output capacitor of the pre-
ceding regulator or DC/DC converter, Lf , Cf and Rd form the
damped filter.
However small, the 68nH inductor adds 15dB of attenuation at

2MHz while the resistor reduces peaking by 14dB to less than 100mdB
at a loss of only 68mW worst case. While one such a stage should pro-
vide sufficient ripple rejection, provisions are taken to apply such a
filter both after and before the regulator.
4.2.4 Sinking capability
One easily overlooked aspect of regulators is their inability to sink

current. Neither the DC/DC converter nor the regulator are able to
do so, yet it is necessary in order to meet the settling time specifica-
tion of ±10mA and ±15mV in 1ms. Even if the supply has no external
capacitive load the internal capacitors needed for filtering and stabil-
ity will amount to some 20 − 40µF. With little to no sinking capability
a load of 50kΩ has a time constant of τ = R · C = 50kΩ · 30µF = 1.5s.
When the regulator cannot track the downgoing setpoint due to

its limited sinking ability the analog control loop is broken; the con-
troller accelerates towards saturation at its negative supply rail. This
effect may be utilized by triggering a current-sinking BJT when the
controller undershoots. This effectively provides a class-B stage as

shown in figure 12. R1 is needed to limit transient current and im-
prove controller stability. This simple system simultaneously ensures
a fast fall-time at the output and a closed control loop during tran-
sients.
BUF
R1
Co
Q1
Figure 12: Current sinking circuit.
4.2.5 Headroom sensing feedback
The converter must sense the voltage across the regulator to adjust
its output. This sensing can be achieved with a simple difference am-
plifier and may be discrete or integrated to save space such as the
INA597 [12]. It is most critical that this additional system does not
disturb the transfer of the DC/DC converter control loop. To ensure
that this feedback loop operates as close to the original application
as possible C1 is added as shown in 13. This ensures that for higher
frequencies the difference fed back to the dc/dc converter is the dif-
ference between the regulator input and ground. The resistors are
chosen such that Vref,DC/DC translates to 1V across the regulator.
3k9 6k 12k
LDO OUT
C1
6.8n
INA597 FB
3k9 6k 12k
LDO IN
Figure 13: Headroom sensing amplifier.

24 power section
4.3 test results
As described, the key parameters of the power section are it’s effi-
ciency and output noise contribution in the form of ripple. A sec-
ond requirement is that it needs to be fast enough to follow the con-
troller’s Vset .
4.3.1 Efficiency
Efficiency of power delivery is shown in figure 14. The power re-

quired by the system at an output setpoint of 0V, 0A is substracted
from the equation. This is approximately 2.3W without the embedded
heater. Several observations can be made:
• It’s low efficiency at low output voltage is not surprising, since

the LDO always dissipates the power corresponding with 1V.
This limits the efficiency to 50% at Vo = 1V.
• Full power efficiency equates to 86%. 1W can be attributed to

the LDO, and the remaining 1.6W are copper losses, filter losses,
setpoint driver losses, but mainly losses at the DC/DC con-
verter. We can conclude that the efficiency of the DC/DC con-
verter alone must be in excess of 94.6%, which is excellent.
• As expected the 100mA efficiency is lower because all systems

must operate while little power is delivered.
• Losses associated with power delivery are never more than 2.6W,
which is a manageable amount for PCB based heatsinking with
convection cooling especially since it is mainly divided over two
components.
Figure 14: Power delivery efficiency.

4.3 test results 25
4.3.2 Ripple rejection
Since it is easier to evaluate filter performance at larger signal levels,

measurements are taken from the LPF between the DC/DC converter
and the regulator. Ripple waveforms are shown in figure 15.
10
6
voltage (\mV)
-2
DC/DC output
Filtered
-4
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
time ( s)
Figure 15: Ripple attenuation of 1st LPF stage.
The figure clearly shows excellent performance; the peak-to-peak

ripple is attenuated 24x (27.6dB) or more, as the output noise level is
near the noise floor of the oscilloscope.
The switching frequency is strongly attenuated, but a higher fre-

quency component of approximately 25MHz is present on the output
of the DC/DC converter. This is neither a harmonic of the switching
frequency or an expected resonance frequency. It is likely interaction
between parasitics. Further development may focus on removing this
component, but since there is no trace of it in the filtered output the
result is considered sufficient.
Since the PSRR of the regulator exceeds 55dB the remaining rip-
ple contribution should be 1.6µVrms . The filtered ripple increases to
3mVpp at low loads when the switching frequency is reduced. It is
attenuated significantly less by the LPF, but is more easily attenuated
by the regulator. In this mode of operation the ripple contribution
should not exceed 3µVrms .
Therefore, no second filter stage appears to be needed. The validity
of this statement will be further evaluated in the overall noise sec-
tion, as Ṽout of the actuating system cannot be measured without
involving the controller and specialised equipment.
26 power section
4.3.3 Settling time
Settling time is evaluated with an average load of 250Ω following a

step from 1V to 15V. This ensures that no boundary issues occur since
falling settling speed is reduced below 200mV due to VCE,sat of the
sinking transistor.
Figure 16 shows that the step response of the system is limited

by the controller and not the DC/DC converter. The pre-regulator is
able to supply enough headroom voltage even during transients. This
may change with larger loads, when the current limit of the converter
comes in to play as it also needs to charge filtering capacitors that are
part of the system. If this is an issue, the heavier variant of the LT8608,
the LT8609 may be used instead. It is capable of supplying 3A instead
of the 1.5A of the LT8608.
18 18
Out
DC/DC
16 16
14 14
12 12
voltage (V)
10 10
8 8
6 6
4 4
2 2
0 0
0 0.2 0.4 0.6 0.8 1 0 0.2 0.4 0.6 0.8 1
time (ms) time (ms)
Figure 16: 1V/15V step response. t = 0 Denominates DAC data latching.
Charge remains in the output capacitor of the DC/DC converter

after a falling step. This charge is slowly reduced as output power
is delivered. So far there are no indications that this influences pre-
cision settling time or accuracy, so there is no need to dispense of
this charge in a manner similar to the the discharge of the regulator
output capacitors. To verify this assumption at a µV level requires
equipment that is currently unavailable.
The step response also shows that the speed of the entire system
is fast enough; after new setpoint data latches into the DACs at t = 0,
the requirements in table 2 give 1ms to reach ±15mV of the final
value. This is reached around t = 900us even with a near-full-scale
step.
4.3 test results 27
4.3.4 Conclusion
We may conclude that the power delivery subsystem meets the spec-
ifications. However a full conclusion regarding output ripple and
EMI/EMC cannot be drawn without evaluating the controller also,
which will be evaluated in section 5.5.5.
Further improvements could involve a close examination of the

effect of the remaining charge, as well as removal of the 25MHz oscil-
lations on the output of the DC/DC converter.
F O R WA R D C O N T R O L
5
5.1 goals and topology
The forward control general circuit is depicted in figure 17. The func-
tion of the controller is as follows:
• Accept digital voltage and current setpoints and impose them

on the load.
• Smoothly respond to setpoint changes under all load conditions;

the system should settle to ±15mV within in 1ms.
• Quickly reject load disturbance w.r.t. the setpoint due to varia-

tion in loading. In other words, minimize output impedance.
• This system is mainly responsible for noise performance in the

f1 < f < f2 frequency band.
• The system has more than one setpoint. Both a voltage and cur-
rent limits are applied, and the appropriate limit must be en-
forced.
Figure 17: Controller circuit.
29
30 forward control
As stated in chapter 2, the forward controller only needs to be op-

timized for lowest noise and highest speed. No power needs to be
delivered, while DC accuracy and linearity are the domain of the dig-
ital feedback subsystem.
If 1/3rd of the noise budget is allocated to the controller, the noise

density limit equals:
q
1
3· 10µVrms √
Ṽo = √ = 1.3nV/ Hz (4)
20MHz
This is a very low noise target for semiconductor devices. We may
neglect the 1/f component as long as fcorner < f0 = 30Hz. Also,
above f3 the noise performance will be dominated by passive filtering.
With a proper filter the noise contribution quickly becomes negligible
for > f1 = 100kHz. Therefore we may re-apply equation 4 with a
more narrow bandwidth:
q
1
· 10µVrms
3 √
Ṽo = √ = 18.3nV/ Hz (5)
100kMHz − 30Hz
And for current noise:
5µArms √
Ĩo = √ = 9.1nA/ Hz (6)
100kHz − 30Hz
This leaves significantly eases the controller noise targets, but the
entire budget should not be spent on this alone. Since only one of
these modes is active at the time, the respective controllers can be
designed separately if the combining circuit is properly chosen. The
most common way is to use diodes with a pull-up current source as
shown in figure 17. The diodes ensure the output is set by the con-
troller enforcing the lowest limit, although it should be noted that the
other controller will saturate towards its positive supply rail if this
is not prevented. This saturation will show itself when the controller
changes from constant current mode (CC) to constant voltage mode
(CV) or reversed. To combat this, a saturation prevention circuit us-
ing dynamically switching feedback loops will be employed; however
development of this circuit is not part of this thesis.
5.2 setpoint dacs
The main characteristic of the DACs that generate the setpoints is

their resolution and noise level. While we could consider the sys-
tem step size as the required effective resolution, the noise level is
5.2 setpoint dacs 31
far lower and this needs to be compensated also. We could use the
RMS noise value as minimum resolution, but VDACstep need not be
smaller than Ṽ as Ṽcorr 6= VDACstep . This is illustrated in figure 18
and equation 7 where the the RMS integral is applied to the error
waveform resulting from the DAC taking corrective action to counter
the system drift.
Z1
s
Ṽcorr 6 (t − 0.5)2 dt · LSB = 0.288LSB. (7)
0
The ’6’ comes due to the fact that the sawtooth waveform will
be smoothed by the limited bandwidth of the system, but since we
cannot know the frequency of the sawtooth1 no fixed correction factor
can be applied.
LSB Thresholds
Uncompensated drift Corrective action

Residual error
+1
0
-1
Time
Figure 18: Error waveforms due to DAC setpoint correction.
If the entire noise budget is spent on corrective action noise (Ṽcorr )

the minimum resolutions of
15V · 0.288
Vres > log2 [ q ] = 19.5Bits (8)
1
3 · 10µV
and
1A · 0.288
Ires > log2 [ 1
] = 16.6Bits (9)
3 · 5µA
are required. The highest resolution available for instrumentation

grade DACs is 20 bits [1]. Therefore no less than one third of the
noise budget can be spent on corrective action. The MAX5719[2] is
simultaneously the cheapest ADC with the lowest noise density and
the fastest settling time. Its DNL is good enough to uphold the valid-
ity of equation 7. More expensive DACs have better INL and stability,
which are of no concern for the controller. The MAX5719 therefore
ideally matches the design goals of the forward controller.
1 The time between DAC setpoint transitions depends on the drift speed, which will
not be constant, and LSB size.
32 forward control
5.3 voltage mode controller
The voltage mode (CV) controller is relatively straight forward; it is

a standard band-limited amplifier with a DC gain of 4.266.... With
Vdac,max = 4.096V, this results in Vo,max = 17.4763V. Strictly speak-
ing 15V would suffice. However there are offsets, on-board copper
losses and when the sense functionality is used, system-to-load wire
losses to overcome. With an additional 2.5V of controllable range
most reasonable copper losses can be overcome. The somewhat odd
value is chosen for computational ease; in a 20-bit system 6 DAC
LSBs match up with exactly one LSD: 100µV 6 · 220 = 17.4763V. Correc-
tive action noise is not significantly degraded; only 0.22 more bits are
needed.
5.3.1 Ground forcing
Arguments can be made against forcing the negative terminal of Vset

voltage source by OP1 in figure 19. The low frequency error due to
the current sense resistor could be removed by the global feedback
loop, and high frequency components can be coupled to reference
nodes. However at the crossover frequency neither mechanisms are
properly in control. Fortunately the DAC allows its ground reference
terminal to be lifted up to +0.3V above the ground power terminal it
needs to share with the Iset reference for communication purposes.
If this condition can be met both the circuit for ground forcing can be
implemented in a very simple manner and the dynamic performance
of the system can be greatly improved. It is preferable to let the analog
circuit handle the output transients since its response is much faster.
Fortunately all design choices of greater importance2 allow this

simple implementation to be used, as shown in figure 19.
5.3.2 Detailed design
Cf determines the settling response as BWLPF >> BWCT RL . For

stability the high-frequency feedback is taken before the LPF as this
eliminates the phase shift introduced by the LPF from the controller
stability equation. DC feedback is taken from the output to ensure
high accuracy.
Ru +RL
RL = 4.266..., therefore determining their value is relatively
straight forward. Once the Cf /Ru ratio is found the absolute values
can be reduced until the resistor noise contribution is no longer dom-
inant. Then the following holds true:
2 A maximum resistor voltage due to resistor power dissipation and a minimum volt-
age due to ADC SNR shown in equation 13
5.4 current mode controller 33
Figure 19: Voltage control section.
• In the < f1 band the noise is removed through recalibration.
• In the f1 < f < f2 band DAC noise is amplified by the DC gain.
• In the f2 < f < f3 band output noise is dominated by the noise

voltage of the opamp, which is not amplified due to Cf and Cd .
• For > f3 noise is strongly attenuated through passive filtering.
Choosing the op-amp is easy when keeping the design goals of

the controller
√ in mind; ADA4898 [14] has the lowest noise voltage
(0.95nV/ Hz) and highest bandwidth (UGBW = 100MHz) of the
opamps that are suitable for a reasonable price. Further details are
unnecessary for this thesis, and the design approach allows for a the-
oretical output noise voltage of merely 3µVrms in the full system
bandwidth; this should take less than 10% of the noise budget.
5.4 current mode controller
The main difference between voltage mode control and current mode
control is the variability of feedback gain, since it is dependent on the
load. Therefore it is important to define under which load conditions
the target specifications should hold.
stability The feedback ratio is maximized at unity when the load

is shorted. This can occur either directly or with a small-signal equiv-
alent such as a large capacitor. This is the worst-case scenario under
which the system must remain stable. Instability with high-Q (> 5)
34 forward control
or negative resistance loads is generally accepted behaviour in labo-

ratory power supplies. Including them in the normal operation area
where performance specs must hold will greatly increase the diffi-
culty of design.
accuracy When Rl is very small, the power supply cannot be

expected to exhibit current noise < 5µArms . The current is controlled
though output voltage, so for > f2 there is noise present at the output
which is not under the control of the current controller. For decreasing
Rs < 2Ω, Ĩ 3 will increase rapidly as Ṽ dominates.
5.4.1 Scaling
Scaling the setpoint voltage to the control parameter is much simpler

for CV mode; The output quantity (voltage) is of the same type and
larger than the setpoint quantity (voltage), therefore a simple resistive
feedback divider suffices. For CV mode the output quantity is current
which must be compared to a voltage.
Due to a lack of accuracy in active devices current sense resistors

are the only reasonable option available. The current sense resistors
with lowest lifetime drift are Vishay’s VCS1625 series with a load-
life stability of 200ppm and a temperature coëfficient of 2ppm/K.[11].
These are only commonly available as 10mΩ, 50mΩ, 100mΩ, 250mΩ
or 500mΩ before exceeding their power rating at the 1A design spec.
Since the resistor is shared with the digital correction loop, the ADC
sets Rs > 14mΩ based on its SNR as shown in equation 13. This
shared use makes minimizing drift in the resistor doubly important.
However from a control standpoint the most ideal solution would
be to use a sense resistor value (≈ 3.9Ω) such that the voltage drop
equals the setpoint voltage, but with Vset,max = 4.096V and Imax =
1.05A4 the power loss (4.5W) is unacceptable. Lower resistance val-
ues require setpoint voltage attenuation to compare signals at lower
amplitude as in figure 20, or amplification of the Rs voltage to match
the setpoint voltage as in figure 21. This scaling circuit will contribute
more noise as greater gain or attenuation is needed.
The total noise figure is the (vector) sum of the setpoint voltage
noise and the feedback path noise. The noise contribution of the scal-
ing circuit is therefore equal whether it is scaling up or down; there-
Ṽspec
3 2Ω = 5µArms .
4 1µA/LSB · 220bit = 1.048576A FSR gives great computational ease at the cost of only
0.07bit resolution with respect to exactly 1A.
5.4 current mode controller 35
Rs
Figure 20: Setpoint attenuation with A = 4.096V < 1.
4.096V
Figure 21: Current sense amplification with G = Rs > 1.
fore noise performance is of no consequence when choosing where

to apply scaling.
The best scaling location is found from a control theory point of

view. Consider a setpoint change scenario. The controller initially
responds as an unity gain follower to the (filtered) DAC setpoint
changes due to the pole created by Cf . Thereafter the controller re-
moves any residual error through integration by Rf and Cf ; this is
a slower settling response towards the desired output. To minimize
the total settling time it is desirable to maximize this initial ’jerk’. A
τf < τd restriction is required to prevent output voltage overshoot.
Both effects are beneficial and have greater impact when the con-
troller operates on larger signal voltages. Therefore the implementa-
tion of figure 21 is the better choice with respect to attenuation of
the setpoint voltage. The resulting circuit is shown in figure 22. Its
performance was verified in LTspice, where a √circuit design using
state-of-the art Op-Amps with Ṽin = 0.85nV/ Hz (where needed)
36 forward control
and Rs = 0.1Ω 5 was able to achieve the required noise performance.

While possible with Rs = 0.05Ω, this value is twice as costly as
Rs = 0.1Ω and it leaves little to no room for unforeseen noise con-
tributions.
Figure 22: Current control section.
5.4.2 Noise coupling
Due to the low voltage level of the signals coming from Rs , kelvin
sensing must be applied even if the voltage levels are closely related.
A coupled path of only 10mΩ conducting an unrelated 10µA tran-
sient spike may create an error of merely 100nV. However this causes
an Ĩ = RṼs = 1µA error spike if coupled into the negative sensing
trace. While the kelvin force op-amp may significantly add thermal
noise, the random parameters of previous example are not abnormal
and 10mA digital or analog signal transients are not unexpected. The
thermal noise contribution is much easier to design around than at
the board level design, and the buffers ensure that no current flows
through the Rs sense terminals which are shared with the digital cal-
ibration scheme.
4.096V
5 And thereby A = Rs = 40.96 → Ru = 39.96 · Rd
5.5 test results 37
5.5 test results
5.5.1 Controller mode switchover, peaking and stability
A few aspects of operation can be assessed from figure 23 where the

power supply is loaded with a low-ESR 100µF capacitor and set to
Iout,max = 30µA. The output voltage is controlled to step from 50mV
to 150mV at t = 0s. Transient effects are magnified in this scenario
due to the extremely low current setpoint. The following observations
can be made.
• The power supply is stable with large capacitive loads in both

CV and CV mode, as can be seen from the flat and rising lines
respectively. No oscillation occurs.
• The pole caused by Cf in figure 19 causes the initial voltage

peak. This peak will not exceed the voltage setpoint value, yet
this behaviour may or may not be desirable.
• This peak over-triggers the constant-current mode controller

which takes proper control after a transition period. During
this period Cload discharges due to internal loading, but the
discharge booster of figure 12 is not triggered.
• Once the CV to CC transition is completed the output voltage

rises in accordance to what is expected from a 30µA current into
an 100µF CL .
• When the output voltage reaches its new setpoint, a CC to CV

mode transition occurs with less than 4mV overshoot. This low
figure is made possible due to the anti-saturation circuitry em-
ployed.
• There is no peaking at the CC to CV mode transition since there

is no setpoint change and therefore no transient propagation
through a high-frequency pole. This behaviour is representative
of operational mode change in absence of a setpoint change, i.e.
through changes in load.
5.5.2 Step response
From the small-signal step response in figure 24 and 25 we can also

observe that the step response is sufficiently fast and unimpeded by
the slower DC/DC pre-regulator. The slight undershoot following a
falling setpoint comes from discharging Co from figure 12. The con-
trol signal needs time to recover from Vo − Vbe to Vo , but this be-
haviour remains within the 1ms settling specification.
38 forward control
160
140
120
voltage (mV)
100
80
60
Load voltage
40
-50 0 50 100 150 200 250 300 350
time (ms)
Figure 23: Voltage step response with current-limited slewing due to capac-
itive load.
2.5
2
voltage (V)
1.5
1
V out
LDO V in
0.5
-0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
time (ms)
Figure 24: 1V rising step response with small load (220Ω)
5.5.3 Load rejection
While the 200mA, fast-flank (> 100mA/µs) of figure 26 is not rep-

resentative for a scenario where the precision performance of the
power supply is relevant, it does give useful insight in its perfor-
mance. From the figure we may deduce that Re(Zout ) ≈ 10mΩ and
Abs(Zout ) = 100mΩ which is quite low compared to the competi-
tors listed in table 1. Re(Zout ) applies to the controller only as preci-
sion correction will reduce this further. While the error caused by the
transient exceeds 15mV, this error scales linearly with the magnitude
of the current pulse and depends on the output capacitance of the
supply. In a scenario where such pulses are applied we may expect
additional capacitance near the load, reducing the magnitude of this
spike.
5.5 test results 39
3
V out
LDO V in
2.5
voltage (V)
1.5
0.5
-0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
time (ms)
Figure 25: 1V falling step response with small load (220Ω)
25
20
15
10
voltage (mV)
-5
-10
-15
-20
V out
-25
0 10 20 30 40 50
time (ms)
Figure 26: Loading rejection with the system operating at 2V, 500mA re-
sponding to a current load decrease of 200mA lasting 30ms.
5.5.4 Noise
The noise requirement is arguably not only the most ambitious, but
also the most difficult requirement to verify. To make best use of the
equipment available a low-noise amplifier (LNA) was developed as
detailed in appendix B.
The actual performance after extensive tweaking is shown in figure
27. The graphs are recorded separately with the only change being
that the output of the system was shorted with a short wire directly
across Co for the upper figure, and the lower figure shows the noise
as measured with the power supply operational.
There are several hypotheses for both the random and periodical
behaviour, but further investigation and improvements will take sig-
nificant time and equipment currently unavailable. Through careful
elimination there are several observations and estimations that could
40 forward control
be made based on the many measurements performed on both the

LNA and the system under test.
• when triggered synchronously with the DC/DC converter and

the average of 64 cycles is taken, there is little to no (6 6µVpp )
visible residual ripple from the DC/Dc converter. Some of this
may be due to capacitive coupling across the isolation barrier
of the trigger signal isolator required to reduce ground loop
interference to the oscilloscope.
• The 200µVpp , ≈ 27kHz ripple dominates the automated RMS

calculation. Its frequency is exhibits some jitter and its source
is unknown, but all chopping amplifiers have been eliminated
from the signal chain. Unfortunately this results in an highly
unreliable Ṽrms reading.
• There is a smaller, somewhat triangle-wave-like signal present

which can be fully traced to the LNA.
• Based on the comparison between the two graphs, we can only

conclude that the output noise may be close to the target value
but clearly > 10µVrms even without considering low-frequency
noise.
The large amount of time and effort needed to obtain measure-

ments of the quality shown above predicts a significantly larger amount
of work which needs to be done to fully characterize the noise perfor-
mance of the system. Therefore the full characterization is postponed
for further work.
Noise graph with shorted LNA input
100
voltage ( V)
-100
-60 -40 -20 0 20 40 60

time ( s)
Noise graph monitoring at 4V/100mA
100
voltage ( V)
-100
-60 -40 -20 0 20 40 60

time ( s)
Figure 27: Short-term noise measuring both a short and Ṽout operating at
4V/100mA.
5.5 test results 41
5.5.5 Conclusion
We may conclude that the step response of the system is as predicted.

We may compare the results to the Keysight B2961A, which is the
nearest relevant competitor and market reference.
• Setpoint change: The performance quoted by the market refer-

ence6 is achieved ≈ 8 times faster.
• Load Rejection: The market reference reaches the settling band

of ±20mV within 50ms. For an equal load step applied to the
new design, the peak error barely exceeds this band (25mVpk )
while being reduced to 2mV within 10ms. This is a significant
performance increase.
• setpoint overshoot: There is no setpoint change induced over-

shoot, compared to ± − 0.1% + 10mV.
• Capacitive load: Unlike the market reference, the controller is

stable with any size capacitive load without needing a separate
’high capacitance mode’.
• Natural mode overshoot: Mode transition overshoot caused by

load change is not quoted by any of the competitors. But even
when it is assumed to be equal to the setpoint change, the per-
formance of the new design is significantly better with only
±5mV over the entire range.
We may therefore conclude that the transient response and the

anti-saturation mechanism significantly outperforms the market ref-
erence.
On the other hand, it has become clear that the noise requirement
is ambitious to the extent that the design and verification of this per-
formance has taken up most of the design and test phase without
truly conclusive results. While the preliminary results are promising,
further investigation is needed.
6 ±0.1% in 80ms [7]

CORRECTION FOR ACCURACY
6
The circuit in figure 5 performs voltage error correction of the system
described in chapter 5. Since the design parameters of the scaling
circuit are determined by the ADC, the ADC is selected first.
6.1 the adc
The ADC needs to be fast enough to remove drift, 1/f noise and main-
tain accuracy. All ADCs with the required maximum INL of 6ppm
have a resolution in excess of 23 unipolar1 bits, which gives more
than sufficient resolution and computational ease. Therefore this con-
sideration is of little concern.
16.777V
Vres = = 2µV/LSB << 10µV (10)
223bit
1.0486A
Ires = = 125nA/LSB << 5µA (11)
223bit
Of greater concern is SNR. Since the ADC is used to correct low-

frequency errors, Ṽi,adc determines Ṽo,<f1 . While the ADC with the
highest applicable SNR is the LTC2508-32 with 136dB, its limited
flexibility2 make it difficult to implement. The second best ADC, the
ADS1282 with an SNR of 130dB, is quite the opposite in this regard.
It offers a wealth of flexibility and thereby a solution of at lower ex-
pense. Samples can be further averaged in software should SNR be
insufficient3 .
The noise is mostly determined by the gain factors of scaling cir-

cuitry to match Vout,max to the ADC Full-scale range (FSR). Its FSR
is set at 3.35V/PGA. With eq.1 from the datasheet [13] and the cir-
cuit described in section 5.4.1 the noise contribution of the correction
circuit can be determined:
SNR 130
Vref · 10− 20 · Gs 3.35V · 10 20 · 20
Ṽo = Ṽi,ADC · Gs = √ = √ = 3.74µVrms
2 2 · PGA 2 2·2
1 These ADCs have bipolar inputs, so one bit is lost to the unused sign.
2 Power supplies, CM and DIFF input range, communication and reference, etc for
both the ADC and the scaling circuit.
3 This comes at the cost of reduced datarate.
43
44 correction for accuracy
(12)
Since this configuration utilizes the ADC to the best of its capability
it shows that this ADC is a suitable choice for the correction loop. The
current feedback has more design freedom; after all Rs can be chosen
such that a larger signal is available. Using the settings optimal for
voltage measurement as it is has the most stringent requirements, the
minimal value for for Rs is as follows:
SNR 125dB
ṼADC V · 10− 20 3.35V · 10− 20
Rs > = √ ref = √ = 14mΩ
Ĩspec 2 · 2 · GPGA · Ĩspec 2 · 2 · 16 · 3µARMS
(13)
This shows that current noise can be sufficiently corrected by the

ADC without adding excessive noise.
6.2 the references
Both the ADS1282 and the gain calibration system require a refer-
ence. The most accurate references available are the LTZ1000 [21] and
LM399 [18]. Based on their long-time drift and noise performance,
the LTZ1000 remains as the only option capable of providing the per-
formance required.
While the ADC may be driven by a dedicated reference, this is not

advantageous for several reasons.
• The drift of the separate reference is removed through calibra-

tion for voltage only. Doing so for the current measurement
require many measurement and calculating steps to be taken,
inviting errors at every step. Since İ is already mainly deter-
mined by the long-term stability of Rs , the stability of this sec-
ondary reference is less important but still of impact to İ.
• An ADC reference voltage derived from the main reference al-

lows for far more freedom in ADC reference voltage; hence
Vref,ADC = 3.35V can be chosen which is desirable for optimal
utilization of range and computational ease.
• The RMS noise below f1 of the LTZ1000 is exceptionally low

at Ṽ = 1.6uV [21]. A low-noise reference is desirable as Ṽref
affects total system SNR. Even when the scaling circuitry noise
is included the total noise of a dedicated reference will be at
least 5x more.
• The cost of the scaling circuitry is ≈ 4$ and adds around 4ppm/o C

of gain drift. The reference with lowest noise and comparable
drift still has significantly more Ṽ and costs over 14$.
6.2 the references 45
Therefore a dedicated reference increases price without a corre-

sponding performance improvement. The reference scaling circuit
used is depicted in figure 28. Drawing current from the reference
is not advised, hence the buffer Op-Amps. These can also be used
to accurately sense the voltage at the resistor and reference termi-
nals. However the output voltage is not exactly as calculated in equa-
tion 14 due to the (stable) ADC input impedance and component-
to-component variations; for example 7.0V 6 Vz 6 7.5V, or 7.25V ±
3.5%.
Rd1 + Rd2 1.24kΩ + 1.24kΩ

Vref,ad = Vref · ≈ 7.2V · = 3.52V (14)
Rd1 + Ru 1.24kΩ + 3.92kΩ
Rd is split to comply with the common-mode restrictions of the
ADC>[13].
Figure 28: Scaling down the main reference for the ADC. Rf = Ru ||Rd 1.
6.2.1 Practical notes
filtering Reference or signal filtering is an adapted version of

the filtering as applied in the datasheet. The reference is filtered some-
what differently, specifically without two identical Rf . Since the resis-
tive divider already presents an output impedance nearly identical
to the reference used in the datasheet, Rf is chosen to provide equal
impedance to the filter network and the ADC and the second Rf can
be omitted.
ltz1000 Actually getting the quoted performance from the LTZ1000

is easier said than done and may involve ’Terror and Arcana’[22]. Sev-
eral other components and factors contribute to the total error of the
reference. These components may also drift with time and tempera-
ture. In order to mitigate part of these concerns not just the internal
heater of the LTZ1000 is engaged but the entire system, including
its biasing circuitry, is enclosed in a shielded area with temperature
stabilization. By embedding the heater this circuit uses only common
components and manufacturing techniques. It may offer a low-cost al-
ternative to common temperature stabilization techniques, but this ex-
perimental addition may not be necessary for proper function or the
precision required for most applications. Therefore this component
of the system is not discussed in detail in this thesis. The other factor
is PCB layout, but proper layout techniques are well represented in
literature. [8, 9, 15]
6.3 voltage sense interface
While the ADC has a PGA and a 2:1 differential multiplexer built-
in, the input voltage range of these components is not large enough.
Therefore these components cannot be used to perform full system
calibration. The design requirements of the circuit performing these
functions are as follows:
• Linearity below 2ppm. The remaining 4ppm are budgeted to
the ADC. Low initial accuracy through offset and gain errors is
permissible, but should not hamper calibration.
• The amplifier section must scale the output into useable range
of the ADC; an internal PGA setting of 1x or 2x is preferred, as
these settings do not reduce ADC performance.
• Its output voltage should settle to full accuracy faster than 1/fdata
to avoid gain errors dependent on relative switching time.
• [Vs+ − Vs+ ] > 15V, the output design range of the power sup-
ply.
• At least 0V 6 Vs− 6 Vs+ 6 17.5V to allow the feedback system
to measure the output under all conditions it can enforce.
• In order to avoid errors when sensing voltages at nodes with
Zi 6 1kΩ, the current into the sense terminals may not exceed
50nA under normal conditions.
• CMRR needs to exceed 123dB so that the common mode range
of the sense terminals is independent of the output voltage with-
out affecting accuracy.
6.3.1 Multiplexer
Selection of the multiplexer is fairly simple. Since the analog signals

are differential a 2x(4:1) multiplexer is needed, and a wide range of
6.3 voltage sense interface 47
such devices designed for instrumentation purposes is available. Of

those capable of handling the input range required none have on-
state resistance that is large enough to amplify input current noise
nor bias current enough to cause even remotely significant errors. Of
the remaining ICs with low enough leakage currents, the ADG5249F
was chosen due to the protection it offers. The force and sense leads
of the power supply are user-accessible and are all connected to the
multiplexer as shown in figure 29. The sensitive circuitry following
the mux is protected from continuously applied over-voltage up to
±50V and ESD events. If the output-enable signal to the switch is
overridden by the overvoltage detection flag from the ADG5249F, the
LDO section is also protected from such events.
The common mode voltage for zero calibration is also Vref =

7.2V ≈ Vfsr /2 since this is the most likely case in normal operation.
Vref was chosen as it is close both in voltage and spatially on the pcb.
This also eliminates another reference generating circuit.
Figure 29: Multiplexer and funnel amplifier detailed connection.
6.3.2 Funnel amplifier
The requirements for the amplifier section point towards using a dif-
ference or instrumentation amplifier. Commercially available variants
of these are often hardwired for a minimum gain that is larger than
the desired gain, and are therefore not preferred.4 The few commer-
cially available amplifiers with (G 6 0.1) have insufficient CMRR,
whether they are of the instrumentation or difference type. The via-
bility of an amplifier based on discrete components is limited by the
same mechanisms as their integrated counterparts. Examples in the
datasheet of the matched resistor network LT5400 [19] show that the
required performance is not attainable without manual calibration,
even with the best components available for the task.
Fortunately the specifics of the application allow for a different

type of circuit to be used. The circuit in figure 30 can only be ap-
plied due to the unipolar nature of the input signal, as well as the
bipolar supplies of the ADC. As long as the circuit operates properly
close enough to Vin = 0 for calibration its performance is expected to
be much better than the performance of a common instrumentation
amplifier.
Its other benefits lie in its simplicity; the low component count
compared to the instrumentation amplifier 5 and optimal use of the
strenghts of each component allow for a much greater CMRR and
linearity.
The two op-amps mirror the input voltage across Ru . The resulting
current is passed by the JFET and Rd , therefore the input is scaled
with a ratio of Ru /Rd .
While operation is simple many pieces of the puzzle must come

together for it to work correctly; for example the diode is needed
to keep the signal above the minimum common-mode voltage of
0.5V[13].
The resistors only need to be picked for linearity. The best resistors
exhibit < 0.1ppm/V. Due to the nature of the circuit Rd compensates
slightly for the non-linearity of Ru , and therefore the total maximum
error should not exceed 1.45ppm.
A JFET is chosen as cascode element due to the low leakage cur-

rents the devices are famous for. It should also remain in saturation
under all valid operating conditions and must be of the P type. N-
type JFETs cannot be turned off due to a lack of drive voltage head-
room, as the −2.5V supply rail is used to supply the op-amps also.
4 Persisting in this approach would lead to three gain stages: the instrumentation
amplifier, a postscaling resistive divider, and the PGA or buffer in the ADC.
5 2 op-amps, 2 resistors and a JFET compared to 3 op-amps and 4 resistors for the
equivalent instrumentation amplifier.
6.3 voltage sense interface 49
Figure 30: Funnel amplifier circuit. Guard rings are shown with dashed grey
lines.
While these op-amps already operate in (near) unity gain configu-

ration which optimally utilizes their CMRR and open-loop gain, the
ADA4522 [6] is chosen for its extreme CMRR (> 140dB) and open-
loop gain(> 135dB).
The selection of the filter capacitor may appear a straight-forward

selection for bandwidth, which is true in part. The time constant of
Cf and Rd should be such that the network settles to full accuracy
within 1/fdata . However the parasitic effects of the diëlectric type
should not be underestimated.
• Piëzoelectric pickup in ceramic capacitors (MLCCs) will trans-

late board stresses into a voltage. Board stresses may come from
handling the entire assembly or thermal expansion of the board
and devices around it. Because Cf is placed at the sensitive
input of the ADC, only non-ceramic capacitors are a suitable
choice.[9]
• Diëlectric absorption (DA) when modelled as a parallel RC net-

work with a slow time constant[9], shows itself as an offset that
is a fraction of the average voltage. Therefore this offset will
be removed when f0 << τ1rc . This τrc nor its R are well de-
fined in component datasheets, but τ usually takes several sec-
onds. Therefore it is hard to be sure when this condition is met,
but fortunately film capacitors again also have a low DA which

make a negative impact significantly less likely.
• Cf also needs to have a highly linear leakage resistance. Static,

temperature dependent or large leakage currents are corregible.
However once any of these become non-linearly voltage depen-
dent the dynamic correction is powerless and the part claims
some of the non-linearity budget. The linearity of the leakage
in such devices is generally not documented. Again it is the
film capacitor which also has such little leakage6 that even 10%
non-linear behaviour of this resistance accounts for less than
0.05ppmINL worst case.
Leakage may also manifest in components not generally thought

of as components in the circuit, such as the PCB. Board leakage may
show in errors other than offset: since leakage currents are dependent
on the voltage between the leaking nodes and the surrounding circuit,
they can degrade CMRR also. There are several cases where special
measures are needed.
• JFETs are ideally suited for the pass element application due to
their extremely low Igss , which are guaranteed to not exceed
1nA. This translates to less than 0.85ppm in the circuit used.
MOSFETs have significantly higher leakage7 and are therefore
unsuitable unless the system is designed for larger full-scale
current, which entails unnecessary larger power dissipation.
• CMRR is degraded by leakage from the lower mirrored node

where the current through Ru enters the source of the JFET.
Therefore a guard ring is applied around all contacts and traces
of this node to prevent leakage to nearby traces. No extra ampli-
fier is needed as the REF- input can serve as a guard ring driv-
ing node; its current limit is orders of magnitude larger than the
allowed leakage current of the guarded node.
• Any current injected to the positive output node connected to

the drain of the JFET will also cause errors. CMRR is not de-
graded since the node voltage does not move with either REF+
or REF-. If the voltage on any adjacent trace is assumed static
and the leakage phenomenon assumed linear, all errors should
be removable through calibration. Therefore this node does not
warrant an amplifier-driven guard ring. However, it is little ef-
fort to place a guard ring which ensures all leakage from this
node is shunted in parallel with Rd , a low-impedance and in-
sensitive node. With only a small voltage across the leakage
barrier any non-linear leakage phenomenon is also less likely
6 > 1GΩ [20]
7 Best found had > 20nA, 10µA is typically seen in MOSFETs.
6.4 current sense interface 51
to be significant. Therefore the design depends less on previous

assumptions.
All these requirements can be met in worst-case conditions by com-

mercially available components. Therefore no errors should remain
which together do not exceed the total budget or require manual trim-
ming to do so.
6.4 current sense interface
While the system is responsible for both voltage and current correc-
tion, the scheme described in 2.3 can now only be applied to the
output voltage. Applying the same scheme poses the following prob-
lematic requirements:
• To calibrate for zero current the sense resistor must be taken

out of the output current path. Calibration during active use is
therefore difficult, since switching the sense resistor results in
noise due to a discontinuous output impedance.
• Analog multiplexing is needed at the rated current. Six switches

will take up significant board area; this is without inserting a
temporary resistor to minimize output impedance discontinu-
ity.
dV
• The switches will inject charge and the dt of the driving signals
are cause for EMI concerns.
• Implementing an accurate current reference is significantly more

difficult than designing an equally accurate voltage reference.
Current references do not readily exist and when basing one on
a voltage reference, accuracy is co-dependent on the accuracy of
the subsequent transconductor. The most accurate V-to-I device
available is the resistor; this shows that accuracy is then still
limited by the most accurate resistor available. Whether this re-
sistor is part of the transconductor or is Rs directly makes little
difference on accuracy. This substantially larger current accu-
racy limit shows in the specification of the B2962A in table 1.
In the face of these challenges the choice to depend on the accuracy

of Rs then becomes a reasonable one. This leaves matching the ADC
to Rs . Since the chosen ADC has an internal PGA there is no need
of a scaling circuit, nor a level shifting cirrcuit. The ADC can work
with a ±2.5V power supply with respect to its digital signal ground
DGND; therefore the voltage across Rs is neatly in the middle of its
allowed common-mode range as depicted in figure 31. The built-in 2:1
multiplexer of the ADC allows for easy switching between current or
voltage monitoring.
Figure 31: The straight-forward connection of Rs to the ADC.
6.5 correction
The correction loop sequence is depicted in figure 32. Since current

offset calibration can only be performed when the output is disabled
it is not part of the calibration sequence. The ADC offset is also highly
stable at 20nV/o C resulting in an error of only 0.2ppm/o C. This is
equal to the typical drift of the resistor, and this error component can-
not be removed through calibration. This also applies to gain errors
of the ADC. Therefore no calibration slots are allocated to current
measurement calibrations.
Figure 32: Division of system cycles.
During each system cycle one of the two calibration constants is

updated. Both calibration constants are refreshed every two system
cycles, not accounting for additional filtering to reduce noise. The
point-of-load voltage (Vo,s ) is only measured when it is selected as
the correction loop source. These measures allow for the highest mea-
surement rate of the output parameters, Vo,f , Io and optionally Vo,s .
This cycle is shown in figure 32 with the following abbreviations:
• VOCAL: Voltage offset calibration, removes offset drift in the

feedback chain.
6.6 test results 53
• VGCAL: Voltage gain calibration, removes gain drift in the feed-

back chain.
• VOF: Output voltage force terminal (internal) measurement and

correction when in Force CV mode.
• VOS: Output voltage sense terminal (point-of-load) measure-

ment and correction when in Sense CV mode.
• IO: Output current measurement and correction when in CC

mode.
Calculations and filtering to update the calibration constants can

be performed during the IO measurement cycle.
As a result the feedback chain errors are corrected with a rate of
fdata /6 or fdata /8 and the limiting output quantity is corrected at a
rate of fdata /3 or fdata /4. No devices in the controller section have
significant 1/f noise extending beyond 25Hz. The effective bandwidth
of the ADS1282 equals 0.413fdata or 103Hz; therefore this scheme
allows for fdata = 250SPS where the SNR of the ADC is highest,
cancelling all low-frequency errors.
6.6 test results
During early testing the signal conditioning and multiplexing ap-

peared to be working as intended. After placing the ADC and the
development of its digital interface, it soon came to light that the
ADC filtering had been misunderstood with great consequences.
6.6.1 Data rate
Changing of any of the internal settings8 triggers a re-calibration se-

quence of 63fdata [13] that cannot be prevented. Due to the nature
of the internal filtering, this delay is also needed when switching the
feedback path multiplexer. The ADC continues conversions but when
the external multiplexer is changed the new samples will be averaged
with samples taken with the previous setting of the calibration path
multiplexer, resulting in inter-sample interference (ISI) and meaning-
less output.
The percentage of time spent ’flushing’ the FIR filter can be re-
duced by using higher data rates and performing the necessary fil-
tering at the microcontroller side. This is a significant computational
load for a microcontroller which was not chosen with such a task in
mind, and fdata > 2ksps will render the controller unable to perform
its other tasks. However, now only 31.5ms is lost to ’flushing’ of the
8 PGA gain, f: data, MUX setting, offset and gain calibration registers
FIR filter, after which meaningful samples can be collected and aver-
aged. An average of 128 samples is needed to achieve Ṽ < 5µVpp 9 ,
resulting in a filtered data rate of ≈ 10Hz. A convenient side effect
is that the corrective action noise as depicted in figure 18 now falls
outside of the band defined for the noise requirements, at the cost of
reduced 1/f noise suppression.
6.6.2 CMRR and ISI
CMRR was tested by shorting the sense leads together, resulting in a

differential zero-input. The common mode was then swept from 0V
to 16V resulting in no visible change in average output reading. In
the case of ISI the zero-channel (VOCAL) was monitored while the
adjacent output monitor (VOS ) channel was swept from 0V to 16V,
resulting in no change. The measurement limit rests at 138dB. Both
CMRR and ISI may be assumed to exceed this figure.
6.6.3 Linearity
Since linearity is arguably most dependent on layout and construc-

tion of the funnel amplifier. When the ADC is to be replaced by an-
other 10 the circuit and therefore the layout will change considerably.
Combined with the fact that the equipment needed to reliably test
down to the specified level is also not readily available, there effort of
performing the measurements outweigh the gains. When compared
to a regular 5-digit multimeter or the forward controller linearity, the
feedback path seems to equal or outperform them both. A second
harmonic component of −116dB is expected due to the voltage coef-
ficients of the resistors.
6.6.4 Reference
Testing the long-term stability of the reference is outside of the scope

of this thesis as many works have been written on how to make best
use of the LTZ1000 and the like. The embedded heater was able to
measure and control the board temperature with ≈ 50mK accuracy
over≈ 10◦ C external temperature change; this is a 46dB attenuation.
Once settled the embedded heater may consume as little as 500mW
at ambient temperature to keep the board at an elevated temperature
of 38◦ C.
One interesting observation follows from earlier tests. These were

performed with the LM399 reference (21µVrms ) to reduce the risk of
9 This was measured by setting the external multiplexer to the zero-reference, and
therefore includes noise generated by the funnel amplifier etc.
10 for example, LT2380-24 or LT2508-32
6.6 test results 55
damage to the more expensive LTZ1000 (4.5µVrms ). After mounting

the circuit designed with the LTZ1000, the digitized noise measured
from the ’reference’ channel was noticeably reduced to the extent that
it was almost equal to that of the ’zero’ channel, underlining the im-
portance of using a proper low-noise reference.
6.6.5 Conclusion
Theoretically, the application of a feedback mechanism as proposed

appears to be sound. Sufficient resolution, linearity, CMRR and SNR
systems are available at a reasonable cost and have been constructed
as well as partially tested.
Further work may include:
• Changing the ADC to one that supports higher correction speeds.
• Investigations into board-cleaning techniques for long-term sta-

bility.
• Embedded heater reliability tests with respect to copper con-

duction failures.
• Inclusion of always-on function for the embedded heater to re-

duce reference voltage shifts due to thermal cycling.
F U L L S Y S T E M A N A LY S I S
7
7.1 topology phase
Based on the analysis performed to evaluate the overall design strat-

egy, there appear to be no inherent mechanisms that prevent the sep-
arated design approach from working. Critical components and their
requirements have been identified. There are some caveats which
mostly concern noise; for example it’s performance is spread over
several bands.
7.2 design phase
From the detailed calculations we may observe that the requirements

are obtainable, but require careful planning and best-in-class compo-
nents. Despite the need for these components the cost of the bare
PCB and its components1 does not exceed the targeted $500, and all
calibration can be achieved through software.
Some aspects which were not considered during the topology phase
have shown to be of significant importance to overall success.
• Most notably is the influence of the DAC resolution on the

noise performance. With availability of relevant DACs of lim-
ited resolution the error caused by correction as depicted in
figure 18 becomes a serious limiting factor. Using a fine/coarse
DAC scheme may alleviate this problem; the main drawback
being control complexity and cost. It must be noted that this
is more relevant to systems having increased output range, as
Ṽcor already approximately equals the thermal- and semicon-
ductor noise floor of this 15V-limited design.
• The minimum duty cycle poses a limit to the voltage range of

the system. When the maximum output voltage of the design
increases the raw input voltage must also increase. This causes
more problems at lower output voltages as the converter enters
pulse-skipping or frequency foldback even at voltages that are
considered medium for the current 15V design.
• The CMRR of the funnel amplifier does play a crucial role in

the accuracy performance, and its vital function of matching the
1 Digital systems, interface board and AC/DC converter included, without assembly
expenses.
57
58 full system analysis
ADC to the output range. In-depth investigation following the

topology phase has shown that the CMRR of common topolo-
gies is insufficient. One alternative was proposed.
• A semi-discrete approach as depicted in figure 10 provides in-

sufficient performance. A more costly approach of using an
LDO outside of its intended purpose was necessary.
• Experimentation has shown that lossless LPFs are inefficient in

performing their main electrical function, that of filtering rip-
ple without introducing ringing. Accepting some power loss by
introducing series resistance significantly reduces cost and size
while increasing filtering effectiveness. This is a less attractive
solution for designs with a higher output current rating.
From the design phase we may conclude that the performance level
is attainable with modern day components as long as no unexpected
issues arise during the prototype phase.
7.3 prototype phase
A prototype as shown in appendix A was developed. We may assess

the design on several aspects:
• Noise Providing a measurement setup for noise performance

has proven to be as difficult as producing the design itself, since
the performance of the used equipment must exceed the per-
formance of the DUT. Therefore noise performance is the least
well-verified of all design aspects. In hindsight, the influence of
the reference does make an impact on the measurement noise
and therefore the Ṽ6f0 . Nevertheless, we may conclude that the
estimated noise level of ≈ 30µVrms is near the design target of
10µVrms as well as competitive when combined with the other
performance aspects.
• Precision Precision depends on the linearity and CMRR of the

feedback network. Linearity appears to be feasible with practi-
cal components but has not yet been tested, in contrast to CMRR
which greatly exceeds the design minimum.
• Stability While not verified directly2 , we may logically conclude

that the theories applied allow for the targeted long-term accu-
racy. Dynamic calibration works as intended without introduc-
ing excessive expense or loss of power and therefore overall out-
put voltage accuracy depends on reference stability. The amount
of Ṽ1/f removed by the feedback system is dependent on the
2 verifying 1-year performance would take several units and one year of continuous
use. This type if in-depth testing is outside of the scope of this document.
7.3 prototype phase 59
ADC data rate at the required SNR, and therefore dependent

on the limits of technology.
• Transient response The transient response is thoroughly checked

an exceeds the quoted performance of all relevant competitors,
exhibiting smaller disturbance peaks and faster settling as well
as extremely low output impedance.
• Efficiency Efficiency is not as good as the efficiency of pure

power-oriented power supplies, but these designs feature a 60dB
higher noise level. It comes as no surprise that power must be
expended to reach the noise and accuracy targeted by this de-
sign. All stages of the design have illustrated that contrary to
common belief it is possible to use DC/DC converters in ex-
tremely low noise applications.
• Cost With a design optimized for ease of production it appears

that the manufacturing cost of one unit can be projected to be
significantly lower compared to competitors. This is achieved
through the use of common components and a small PCB with
components mounted on one side only.
Several other theories and ideas with respect to board layout, shield-
ing, filtering, thermal management, digital routing and software have
also been tested which will provide valuable information for the fol-
lowing design stage.
60 full system analysis
7.4 conclusion & recommendations
Both the design phase and the practical phase have yielded valuable
information required to evaluate the usefulness of the proposed topol-
ogy. In many cases the effectiveness of the proposed topology is con-
strained by the available components3 , manufacturing techniques, or
the laws of physics. The resulting hardware could not be fully tested
with the available tools yet the aspects that have been tested have
yielded results in excess of the competing units at a lower cost.
From all these observations we may conclude that the design ap-
proach offers a low cost and efficient approach towards improve-
ments of ultra-precision laboratory power supplies.
In order to reach a marketable design, further development must

include:
• In-depth noise measurement.
• Reference stability tests, since this aspect strongly depends on

PCB layout and post-assembly cleaning.
• Linearity verification.
To improve performance the following developments are advised:
• A separate ADC for current measurement.
• Change of the voltage ADC and its funnel amplifier to improve

the correction rate. Investigating the potential of the LTZ2380
and comparable ADCs is highly recommended.
• Synchronisation of the switching power supplies, microcontroller

and ADCs to reduce EMI.
3 Or the available budget.

S Y S T E M H A R D WA R E
A
The printed circuit board which holds the circuit has been designed
with the following restrictions and guidelines.
a.1 layers
A four-layer design is chosen to facilitate easy shielding and signal

separation, without the significant cost increase incurred with six lay-
ers or more. Vertical partitioning is strongly divided as follows:
• Top The top layer contains all SMD components as well as sen-
sitive signals. Shielded by the layer below. Strong spatial sepa-
ration between digital and (sensitive) analog sections.
• Ground sheet Single-piece ground, no signals or power distri-

bution.
• Heater/Auxiliary layer Contains the embedded heater trace. Sec-

ondary ground layer, also used when less sensitive traces must
cross each other on the top layer. Analog and digital traces are
strictly kept from crossing and keep distance from one another.
• Bottom Power distribution and dissipation, digital signal layer.

No components to reduce manufacturing costs.
a.2 partitioning
Planar grouping is mostly inspired by [17]; the result of this can be

seen in figure 34. Mixed-signal systems are placed on a clear bound-
ary to avoid digital/analog signal interference. Any digital trace pass-
ing beyond these sections must have a high driver impedance (Zdrv >
5kΩ) to avoid strong current transients. Return paths are always op-
timally close through layer 2, the ground sheet.
As a result of this strategy no system-frequency interference could
be detected on the output.
Power dissipating or switching circuits are placed towards the up-

per left corner in figure 34 while the most sensitive circuits are placed
furthest away. These sections are encased with an EMI shield on the
top layer. This additionally equalizes the temperature within and pro-
tects against medium-frequency airflow induced thermocouple errors
[15]. The reference area is separated from the main board with milled
61
62 system hardware
slots and encased with shields on both sides. This results in a refer-
ence layout of figure 33.
• Thermal flow through the board surface is minimized which

improves efficiency and temperature regulation.
• The shields provide an air cushion which reduces external dis-

turbance of the board temperature.
• Thermal gradients on the insulated area are reduced though

reduced contact with its surroundings.
• Mechanical stress and vibrations are reduced.
• Stray unrelated currents cannot pass through the area.
Figure 33: PCB cross-section view of the reference area.
a.3 digital
The digital side of the system is built around the PIC18F46J50 mi-
crocontroller[4]. This microcontroller has the hardware modules and
core capabilities needed.
• Dual SPI One SPI module is needed for local operations such
as DACs, ADCs, memory while the other module is dedicated
to the graphic LCD.
• SPI DMA to allow for hardware-automated interrupt driven

LCD updates.
• Hardware interrupts allow for automated task scheduling with

priority. For example, high level interrupts are ADC conversion
or protection circuits, while low-priority examples are input
push-buttons and the DMA LCD system.
• USB hardware While currently not implemented, USB function-

ality will be developed in the future. Galvanic isolation is added
through ADUM3160[10].
• I/O Sufficiently I/O ports are available to easily connect with

all hardware without additional software complexities.
A.3 digital 63
Figure 34: PCB top view with partitioning marked. Figure 35 shows fished
result.
a.3.1 Interface
The interface hardware, such as the LCD, LEDs and navigation push-
buttons are mounted on a separate tw0-layer PCB. This PCB is devel-
oped separately and also shown in figure 35. The separate PCb allows
for easier mounting to a front panel and is electrically connected to
the main board with a single multi-strand cable.
Several oversights in the digital interface circuits would have greatly

impeded development. These issues have already been solved for the
following development phase, v6.3a1 . In order to maintain usability
of the version developed for this thesis, the v5.6c2 board required an
adapter to communicate with the v6.13 interface board developed for
the v6.3a main board.
1 Sixth board to be produced, third major change since v5, first software version
2 Fifth board produced, sixth major system change after v04, third software version
(C)
3 Interface board designed for main board v06, first version, no software
64 system hardware
Figure 35: Completed test assembly with shield covers removed and addi-
tional SMA test connectors mounted.
T E S T H A R D WA R E
B
Verification of the design had to be performed with limited avail-
able equipment. Since the power supply is self contained, no external
signal generators or power supplies were needed. The measurement
setup involved mostly around the Owon XDS3062A[23]. The band-
width of the oscilloscope (60MHz) allow for analysis of the entire
bandwidth of interest. This alone would not be enough to verify noise,
but is more than enough to verify all forms of transient response.
Most important is the resolution of 12 bits, which is significantly

more than the conventional 8-bit oscilloscope. As a result the mini-
mum input division falls to 1mV 1 . An additional amplifier was de-
veloped to view the smallest signals of the noise bandwidth, This
amplifier should provide +46dB (200x) in the limited band of 10Hz −
20MHz with a sufficiently low Ṽin to leave the 10µVrms noise target
visible on the oscilloscope.
IC2
Ci
Rf
Ri
J1
Ro J2
Cf IC1
50Ω
Rhi
Rlo
Figure 36: Low noise oscilloscope preamplifier schematic.
This schematic is depicted in figure 36. Main amplifier IC1 is sta-

bilized by IC2 as it’s offset is significant. IC2 acts as a low-frequency
1 The noise floor of the oscilloscope has also been lowered in order to make this a
useful setting.
65
66 test hardware
integrator and reduces the input offset to a minimum, which prevents

saturation of the main amplifier as well as the oscilloscope input stage.
Even though a chopper op-amp would seem an obvious choice the
EMI generated by the chopping action within the IC has proven to
show itself in the output. Stability and noise performance of the sys-
tem has been extensively verified with LTspice; the theoretical ṼRT I
should not exceed 5µVrm , but was not met due to yet unknown is-
sues. A time domain graph of the input noise can be seen in figure
27.
b.1 ground loop precautions
To prevent interference from ground loops the oscilloscope operates

from its internal battery and is disconnected from line power. For the
same reason the LNA is designed to run off a single 3.7V Li-ion cell,
where a separate op-amp provides a ground resulting in split rails of
±1.85V. As a result the entire signal path is shielded and does not
form a loop.
b.2 rms measurement
To improve the quality of the RMS value calculation an RMS-to-DC

converter was constructed in a similar manner as the LNA. This con-
verter has proven to work excellently but the output value is domi-
nated by the noise generated by the LNA and gives no meaningful
insights as a result.
Figure 37: LNA with cover removed (left) and battery assembly of the RMS
meter (right) as present on both units.
BIBLIOGRAPHY
[1] 16 and 20-Bit Voltage DACs. MAX5719. Rev. 2. Maxim Integrated.

2019.
[2] 1ppm 20-Bit, ±1 LSB INL, Voltage Output DAC. AD5791. Rev. E.
Analog Devices. 2018.
[3] 20V, 500mA, Ultralow Noise, Ultrahigh PSRR Linear Regulator
with VIOC Control. LT3045-1. Rev. A. Analog Devices. 2017.
[4] 28/44-Pin, Low-Power, High-Performance USB Microcontrollers with
nanoWatt XLP Technology. PIC18f46J50. Microchip. 2011. url:
http://ww1.microchip.com/downloads/en/DeviceDoc/39931d.
pdf.
[5] 42V, 1.5A Synchronous Step-Down Regulator with 2.5µA Quiescent

Current. LT8608. Rev. D. Analog Devices. 2019.
[6] 55V, EMI Enhanced, Zero Drift, Ultralow Noise, Rail-to-Rail Out-
put Operational Amplifiers. ADA4522. Rev. F. Analog Devices.
2017. url: https : / / www . analog . com / media / en / technical -
documentation/data-sheets/ADA4522-1_4522-2_4522-4.pdf.
[7] B2961A/B2962A 6.5 Digit Low Noise Power Source. Keysight Tech-
nologies. 2019.
[8] Kumen Blake. Op Amp Precision Design: PCB Layout Techniques.
Tech. rep. AN1258. 2012.
[9] Analog Devices. Linear Circuit Design Handbook. Elsevier, 2008.
isbn: ISBN-0-916550-28-1.
[10] Full/Low Speed 2.5 kV USB Digital Isolator. ADUM3160. Microchip.
documentation/data-sheets/ADuM3160.pdf.
[11] High Precision Bulk Metal® Foil Surface Mount Current Sensing
Chip Resistor with TCR of ±2ppm/o C and Load Life Stability of
±0.02%. VCS1625. Vishay Precision Group. 2010.
[12] High-Precision, Wide-Bandwidth e-trim Difference Amplifier. INA597.
Rev. A. Texas Instruments. 2019.
[13] High-Resolution Analog-To-Digital Converter. ADS1282. Rev. I. Texas
Instruments. 2013.
[14] High Voltage, Low Noise, Low Distortion, Unity-Gain Stable, High
Speed Op Amp. ADA4898. Rev. E. Analog Devices. 2015.
[15] Martin L. Kidd. Watch Out for Those Thermoelectric Voltages! Tech.
rep. Metrology 101. 2012.
67
68 Bibliography
[16] A.J.M Montagne. Structured Electronic Design. A conceptual ap-

proach to amplifier design. Delft Academic Press, 2018. isbn: 97890-
6562-4277.
[17] Henry W. Ott. Partitioning and Layout of a mixed-signal PCB. Tech.
rep. pcdmag.com. 2001. url: http : / / www . hottconsultants .
com/pdf_files/june2001pcd_mixedsignal.pdf.
[18] Precision Reference. LM399. Linear Technology/Analog Devices.

2010. url: www.analog.com/media/en/technical-documentation/
data-sheets/199399fc.pdf.
[19] Quad Matched Resistor Network. LT5400. Rev. F. Linear Technologiy.

documentation/data-sheets/ADA4522-1_4522-2_4522-4.pdf.
[20] Stacked Metallized Plastic Film Chip Capacitor. ECPU(A). Pana-

sonic. 2015. url: https://nl.mouser.com/datasheet/2/315/
ABD0000C178-947606.pdf.
[21] Ultra Precision Reference. LTZ1000/LTZ1000A. Rev. E. Analog

Devices. 2015.
[22] Jim Williams. Layout Guidelines for Switching Power Supplies. Tech.
rep. AN86. 2001. url: https : / / www . analog . com / media / en /
technical-documentation/application-notes/an86f.pdf.
[23] XDS Series. XDS3062A. Owon. url: http://files.owon.com.

cn/specifications/OWON%20XDS%20Series%20n-in-1%20Digital%
20Oscilloscope%20technical%20spec.s.pdf.
colophon
"An ultra-low noise, fast response, high accuracy and efficiency power
supply for experimental instrumentation purposes."
This document is a Master Thesis for the completion of the Master of
Science Electrical Engineering.
Version: v04-03
Date: November 4, 2020
Author: Roel Zwetsloot, Bsc
Student No. 4205170
University: TU Delft
Mekelweg 5
2628 CD Delft
EEMCS Faculty
Student of the Department of Microelectronics
At DC systems, Energy conversion & storage.
Supervisor: prof. Z. Qin, Dr.eng. prof. P. Bauer

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A N U LT R A - L O W N O I S E , FA S T R E S P O N S E , H I G H A C C U R A C Y

November 4, 2020 – version 1.4

• Prof. Zian Qin for the opportunity, his patience, enthusiasm,

• Both my parents for their motivating support even when grad-

• Jan Trompper for the insightful technical discussions and guid-

• Analog devices, Linear Technologies and Microchip for en-

The purpose of this thesis is to evaluate a top-level topology for ultra-

Whether this is possible hinges on the orthagonality of the top-

2 orthogonal design strategy 3

6 correction for accuracy 43

7 full system analysis 57

Figure 1 Simplest implementation of output control. . . 3

Figure 29 Multiplexer and funnel amplifier detailed con-

Table 1 Various power supplies on the market. . . . . . 15

ADC Analog to Digital Converter

BJT Bipolar Junction Transistor

CMRR Common Mode Rejection Ratio

DAC Digital to Analog Converter

DNL Differential Non-Linearity

INL Integral Non-Linearity

LDO Low DropOut regulator

LSB Least Significant Bit (internal digital variable)

LSD Least Significant Digit (Externally controllable variable)

PCB Printed Circuit Board

POL Point of Load

PSRR Power Supply Rejection Ratio

SMPS SwitchMode Power Supply

TUE Total Uncompensated Error

• The theory behind the design approach will be investigated.

• Design goals are chosen to provide a market-viable result.

• Modules critical to the operation of the design will be investi-

• The result of these designs will be subjected to tests. These tests

• With the information from previous steps the feasibility and

Designing a small circuit that is best at performing all tasks simul-

Figure 1: Simplest implementation of output control.

2.2 global feedback

Separating this functionality across other devices is helpful. Figure

An additional user-accessible load-sense feedback channel is added.

Figure 2: Basic stabilization though digital feedback.

2.3 dynamic calibration

Figure 3: Advanced digital feedback with zero and gain calibration.

• Step 1: The input is connected to zero, and the measured output

• Step 2:The input is connected to the reference with a known

• Step 3: When measurements to the output or POL are performed

Original Offset corrected Gain corrected

Figure 4: Error correction sequence.

The parameters used for correction may be internally filtered over

The calibration scheme of figure 3 maintains it setpoint well if the

The system we have previously described can zero-out tempera-

2.4 thermal immunity

Shielding and repeatable reference temperatures are achieved by

Figure 5: Thermally stabilized implementation of figure 3.

2.5 efficiency and speed

The output section is now shown as a simple buffer amplifier. This

Modern regulators can achieve outstanding low noise levels and

If the PSRR of the regulator is insufficient, additional filtering may

The analog controller still needs to account for fast changes in

Figure 6: Figure 5 modified for higher efficiency and faster control.

2.6 separation in frequency

The proposed design approach has resulted in effective separation of

Figure 7: Frequency ranges.

• DC to f1 , the lower or digital is the range where the digital feed-

should be negligible in this low frequency region. Applicable