Microprocessor System

11/3/2020 Er. Sunil Dahal, IOE, PASHCHIMANCHAL CAMPUS, Pokhara 1

Machine cycle
 8085 has following machine cycle.
 Opcode Fetch.
 Memory Read.
 Memory Write.
 I/O Read
 I/O write.
 Request Acknowledge

11/3/2020 Er. Sunil Dahal, IOE, PASHCHIMANCHAL CAMPUS, Pokhara 2

Timing Diagram
 Necessary steps of Machine cycle can be represented
graphically.
 Such graphical representation is known as Timing
Diagram.
Points to be considered to draw diagram:
1. Identify Instruction.
2. Number of machine cycles.
3. Determine T-States.
4. Determine control signals required for each machine
cycle.

11/3/2020 Er. Sunil Dahal, IOE, PASHCHIMANCHAL CAMPUS, Pokhara 3

Timing Diagram (Cont.…)
 For any instruction:
 1st machine cycle is opcode fetch.
 It takes 4T states for most instruction and 6T for few.
 2nd machine cycle can be memory read (3T) for
memory/(I/O) read/write.
 3rd and 4th depends on the nature of instruction.

 MVI A, 32H
Opcode Fetch(4T) + Memory Read(3T) = 7 T-states.
F R
 OUT FCH
F(4T) + R(3T) + I/O Write(O 3T) = 10T-states.
11/3/2020 Er. Sunil Dahal, IOE, PASHCHIMANCHAL CAMPUS, Pokhara 4
Timing Diagram (Cont.…)
 STA CO5OH
F R R W  13 T-States
 MOV A, B
F  4 T-States
 LDA CO50 H
F R R R 13 T-States

See book p-780 for machine cycle of all instructions.

Gaonkar R, Microprocessor Architecture Programming and
Application with 8085, Fifth Edition

11/3/2020 Er. Sunil Dahal, IOE, PASHCHIMANCHAL CAMPUS, Pokhara 5

Timing Diagram (Cont.…)
 Opcode Fetch

MOV C, A at location
2005H

Location Op-code
2005H 4FH

11/3/2020 Er. Sunil Dahal, IOE, PASHCHIMANCHAL CAMPUS, Pokhara 6

Timing Diagram (Cont.…)
 Memory read

I/O Read????

11/3/2020 Er. Sunil Dahal, IOE, PASHCHIMANCHAL CAMPUS, Pokhara 7

Timing Diagram (Cont.…)
 Memory Write

I/O write??????

11/3/2020 Er. Sunil Dahal, IOE, PASHCHIMANCHAL CAMPUS, Pokhara 8

 Location Op-code

Timing Diagram (Cont.…) 2000H 3EH

 MVI A,32H (Combine the machine cycles) 2001H 32H

11/3/2020 Er. Sunil Dahal, IOE, PASHCHIMANCHAL CAMPUS, Pokhara 9

Timing Diagram (Cont.…)
Class work
Draw the timings diagram for instruction STA 526AH stored at 41FFH

11/3/2020 Er. Sunil Dahal, IOE, PASHCHIMANCHAL CAMPUS, Pokhara 10

Timing Diagram (Cont.…)
STA 526AH

11/3/2020 Er. Sunil Dahal, IOE, PASHCHIMANCHAL CAMPUS, Pokhara 11

Timing Diagram (Cont.…)
Class work
Draw the timings diagram for instruction IN COH stored at 4125H

F R IR

11/3/2020 Er. Sunil Dahal, IOE, PASHCHIMANCHAL CAMPUS, Pokhara 12

Memory devices
 Memory is an essential component of the microcomputer system.
It is used to store both instructions and data.
 Memory is made up of registers and the number of bits stored in
a register is called memory word .
 Memory word is identified by an address .
 If microprocessor uses 16 bit address , then there will be
maximum of 216 = 65536 memory addresses ranging from 0000H
to FFFFH.
 There are various types of memory which can be classified in to
two main groups i.e. Primary memory and Secondary memory.

11/3/2020 Er. Sunil Dahal, IOE, PASHCHIMANCHAL CAMPUS, Pokhara 13

Memory devices

11/3/2020 Er. Sunil Dahal, IOE, PASHCHIMANCHAL CAMPUS, Pokhara 14

Memory Hierarchy
As we go down in the hierarchy
 Cost per bit decreases
Capacity of memory increases
Access time increases
 Frequency of access of memory
by processor also decreases.

11/3/2020 Er. Sunil Dahal, IOE, PASHCHIMANCHAL CAMPUS, Pokhara 15

Address Decoding
 Microprocessor is connected with memory and I/O devices via
common address and data bus.
 Only one device can send data at a time and other devices can
only receive that data. If more than one device sends data at the
same time, the data gets garbled.
 In order to avoid this situation, ensuring that the proper device
gets addressed at proper time, the technique called address
decoding is used.
 In address decoding method, all devices like memory blocks, I/O
units etc. are assigned with a specific address.
 The address of the device is determined from the way in which
the address lines are used to derive a special device selection
signal -- chip select (CS).

11/3/2020 Er. Sunil Dahal, IOE, PASHCHIMANCHAL CAMPUS, Pokhara 16

Address Decoding...
 If the microprocessor has to write or to read from a device, the
CS signal to that block should be enabled and the address
decoding circuit must ensure that CS signal to other devices are
not activated.
Unique Address Decoding:
 The address lines are decoded in such a way that for one
particular address, only one register of memory will be enabled.
 All 16 bit of address should be handled(decoded) properly.
 Don’t care conditions is not allowed.
 It is expensive and complicated but fault proof in all cases.

11/3/2020 Er. Sunil Dahal, IOE, PASHCHIMANCHAL CAMPUS, Pokhara 17

Address Decoding...
Non Unique Address decoding:
 In case of non unique decoding, more than one address can select
same register (Location).
 Some bits are supposed to be don’t care.
 Though it is cheaper there may be a chance of address conflict.
Example:
Unique Address Decoding
A15 A0
1000 0000 0000 0000
1000 1111 1111 1111

CHIP SELECT Register Select

11/3/2020 Er. Sunil Dahal, IOE, PASHCHIMANCHAL CAMPUS, Pokhara 18

Address Decoding...
Example:
Non Unique Address Decoding
A15 A0
10xx 0000 0000 0000
10xx 1111 1111 1111
Here, 10xx have four possible values, 1000 , 1001, 1010, 1011
So, there are four different address possible for same register.
1000 0000 0000 0000  8000
1001 0000 0000 0000  9000
1010 0000 0000 0000  A000
1011 0000 0000 0000  B000

See also: Absolute decoding/Full Decoding, Linear decoding/Partial

Decoding
11/3/2020 Er. Sunil Dahal, IOE, PASHCHIMANCHAL CAMPUS, Pokhara 19
Memory Interfacing
For Memory Interfacing in 8085, following important points are to
be kept in mind.
 Microprocessor 8085 can access 64Kbytes memory since
address bus is 16-bit.
 But it is not always necessary to use full 64Kbytes address space.
The total memory size depends upon the application.
 Generally EPROM (or EPROMs) is used as a program memory
and RAM (or RAMs) as a data memory.
 When both, EPROM and RAM are used, the total address space
64Kbytes is shared by them.
 It is not always necessary to select 1 EPROM and 1 RAM. We can
have multiple EPROMs and multiple RAMs as per the
requirement of application.

11/3/2020 Er. Sunil Dahal, IOE, PASHCHIMANCHAL CAMPUS, Pokhara 20

Memory Interfacing
 We can place EPROM/RAM anywhere in full 64 Kbytes address
space.
 But program memory (EPROM) should be located from address
0000H since reset address of 8085 microprocessor is 0000H.
 It is not always necessary to locate EPROM and RAM in
consecutive memory For example : If the mapping of EPROM is
from 0000H to OFFFH, it is not necessary to locate RAM from
1000H. We can locate it anywhere between 1000H and FFFFH.
 To locate memory component totally depends on the application.
The memory interfacing requires to :
 Select the chip

 Identify the register

 Enable the appropriate buffer.

11/3/2020 Er. Sunil Dahal, IOE, PASHCHIMANCHAL CAMPUS, Pokhara 21

Interfacing Circuit
 Draw interfacing circuit to interface a ROM of 4K size.
4k means 4*1024
2 POWER 2* 2 POWER 10
2 POWER 12
WE HAVE TO USE 12 ADREESS lines for REGISTER SELECT.
Remaining address bit= 16-12=4
A15,A14,A13, A12 are used to generate chip select signal.
Other address bit are used for register select.
Address range for ROM
Starting Address 0000 0000 0000 0000  0000H
Ending Address 0000 1111 1111 1111  0FFFH
chip select 12 bits for address select

11/3/2020 Er. Sunil Dahal, IOE, PASHCHIMANCHAL CAMPUS, Pokhara 22

Interfacing Circuit
 Draw interfacing circuit to interface a ROM of 4K size.

11/3/2020 Er. Sunil Dahal, IOE, PASHCHIMANCHAL CAMPUS, Pokhara 23

Interfacing Circuit
 Draw interfacing circuit to interface 2 RAM of 8K size.
8k means 8*1024
2 POWER 3* 2 POWER 10
2 POWER 13
WE HAVE TO USE 13 ADREESS lines for REGISTER SELECT.
Remaining address bit= 16-13=3
A15,A14,A13 are used to generate chip select signal.
Other address bit are used for register select.
Address range for RAM 1
Starting Address 1000 0000 0000 0000  8000H
Ending Address 1001 1111 1111 1111  9FFFH
chip select 13 bits for address select

11/3/2020 Er. Sunil Dahal, IOE, PASHCHIMANCHAL CAMPUS, Pokhara 24

Interfacing Circuit
 Draw interfacing circuit to interface 2 RAM of 8K size.
.
Address range for RAM 2
Starting Address 1010 0000 0000 0000  A000H
Ending Address 1011 1111 1111 1111  BFFFH
chip select 13 bits for address select

11/3/2020 Er. Sunil Dahal, IOE, PASHCHIMANCHAL CAMPUS, Pokhara 25

Interfacing Circuit
 Draw interfacing circuit to interface 2 RAM of 8K size.
Address range for RAM 1
Starting Address 1000 0000 0000 0000  8000H
Ending Address 1001 1111 1111 1111  9FFFH
Address range for RAM 2
Starting Address 1010 0000 0000 0000  A000H
Ending Address 1011 1111 1111 1111  BFFFH

11/3/2020 Er. Sunil Dahal, IOE, PASHCHIMANCHAL CAMPUS, Pokhara 26

Interfacing Circuit
 Find the address range for three memory device.

11/3/2020 Er. Sunil Dahal, IOE, PASHCHIMANCHAL CAMPUS, Pokhara 27

Memory mapped I/O
 Memory input/ output. It means input is read from memory and
o/p is written to memory.
 Address used in memory mapped I/O is of 16 bit memory
address.
 Memory related instructions such as STA,LDA, STAX, LDAX, MOV,
ADD etc are used.
 Data transfer takes between any register.
 Chip select signal of each device is derived from 16 bit address
lines thus total addressing capability is 64K bytes
 More hardware are required to decode 16- bit address.

11/3/2020 Er. Sunil Dahal, IOE, PASHCHIMANCHAL CAMPUS, Pokhara 28

I/O mapped I/O
 Port input/ output. It means input is taken from i/p device
connected to a port and o/p is given from any o/p devices
connected to o/p port.
 Address used in I/O mapped I/O is of 8 bit port address.
 I/O related instructions such as IN, OUT.
 Data transfer takes between I/O devices and registers.
 Less hardware are required to decode 16- bit address.
 Since only 8bit address is used, at most 256 bytes can be
identified uniquely.
 Generally low order address bits A0-A7 are used and upper bits
A8-A15 are considered don’t care.
 Usually, I/O mapped I/O is used to map devices like 8255A,
8251A etc.

11/3/2020 Er. Sunil Dahal, IOE, PASHCHIMANCHAL CAMPUS, Pokhara 29

I/O interface
 Provides a method for transferring
information between internal storage
and external i/o devices.
Types:
 Serial interface:
 Exchange data with peripherals in serial mode.
 One bit is transmitted at a time.
 Serial transmission is slow.
 The function of serial i/o interface is to deal with data on the bus in
parallel mode and to communicate with the connected device in
serial mode.
 Its data bus has n data lines, the serial I/O interface accepts n bit
of data simultaneously from the bus and n bits are sent one at a
time thus requiring n time slots.

11/3/2020 Er. Sunil Dahal, IOE, PASHCHIMANCHAL CAMPUS, Pokhara 30

 I/O interface
Types:
 Parallel interface:
 The device which can handle
data at higher speed cannot
support with serial interface.
 N bits of data are handled
simultaneously by the bus and
the links to the device directly.
 Achieves faster communication
but becomes expensive due to
need of multiple wires.

11/3/2020 Er. Sunil Dahal, IOE, PASHCHIMANCHAL CAMPUS, Pokhara 31

Interfacing circuit
 Draw interfacing circuit for instruction OUT FCH where FCH is
port address.
 In 8085 the lower order address 8- bit and data bus of 8-bit are
same ie. AD0-AD7.
 So, we need ALE to find address from AD0-AD7
 AD0-AD7 is first connected to ALE which is supplied to 8 input NAND
gate to generate I/O select signal.
 I/O write signal is also generated.
 Both signal are combined by NAND gate to generate latch enable
signal.

FC 1111 1100

11/3/2020 Er. Sunil Dahal, IOE, PASHCHIMANCHAL CAMPUS, Pokhara 32

Interfacing circuit
 Draw interfacing circuit for instruction OUT FCH where FCH is
port address.
FC 1111 1100

11/3/2020 Er. Sunil Dahal, IOE, PASHCHIMANCHAL CAMPUS, Pokhara 33

Interfacing circuit
 Draw interfacing circuit for instruction IN FFH where FFH is port
address.
FC 1111 1111

11/3/2020 Er. Sunil Dahal, IOE, PASHCHIMANCHAL CAMPUS, Pokhara 34

Interfacing circuit
 Draw interfacing circuit for instruction IN 41H and OUT 42H.
I/P port address 0100 0001
O/P port address 0100 0010

11/3/2020 Er. Sunil Dahal, IOE, PASHCHIMANCHAL CAMPUS, Pokhara 35