Ge-on-Insulator Lateral Bipolar Transistors

J.-B. Yau, J. Yoon, J. Cai, T. H. Ning, K. K. Chan, S. U. Engelmann, D.-G. Park, R. T. Mo, and G. Shahidi
IBM Research Division, T J. Watson Research Center, Yorktown Heights, NY 10598
E-mail: jyau@us.ibm.com.

Abstract-We report the first demonstration of thin-base

symmetric lateral NPN bipolar transistors built on 8-inch Ge-on­
insulator (Ge-OI) wafers. A Ge-OI device can achieve the same
collector current as a Si-OI device but at - 460 mV lower V/JE due
to the bandgap of Ge being 460 meV smaller than that of Si.
Lower operation voltage should translate directly into lower
power dissipation. CMOS-like process was used to fabricate
lateral Ge-OI bipolar transistors. The measured collector and
base currents are examined and compared with those of Si-OI
and SiGe-OI devices to shed light on process-related device
physics. The large observed base current at small V/JE is
attributed to recombination at the Ge/BOX interface in the
emitter-base diode space-charge region.

Keywords-Bipolar transistors, SOl lateral bipolar transistors,

Ge-Ollateral bipolar transistors
I. INTRODUCTION
A symmetric lateral Si-on-insulator (Si-OI) bipolar
transistor (Fig. lea)) with a self aligned base contact located
on top of the intrinsic-base region, and base width of about 2
/-lm, was first demonstrated almost thirty years ago [1]. With
the advancement of lithography capability in manufacturing at
present, it is possible to fabricate Si-OI lateral complementary
bipolar (NPN plus PNP) transistors with base widths much
narrower than 100 nm [2, 3] using CMOS-like processes.
Experimental data show that semiconductor-on-insulator
(SOl) lateral bipolar devices have drive-current capability
much higher than that of CMOS [3] and model studies [4]
suggest them to be scalable in lateral dimension like CMOS,
and could havefmax > 1 THz.
In addition, it can be inferred from the current equations
that the operation voltage for a bipolar transistor is
proportional to the energy bandgap of the constituent
semiconductor of the intrinsic-base region [4]. If a Si bipolar
circuit operates with a power supply voltage of 1.0 V, the
same circuit built with SiGe or Ge bipolar transistors can
readily operate with a power supply significantly less than 1.0
V. Recently, a SiGe-on-insulator (SiGe-OI) (-25% Ge) lateral
bipolar transistor was demonstrated to achieve the same
collector current as a Si-Ol device but at -130 mV lower VSE
[5], confirming that indeed the path towards reducing the
power supply voltage for bipolar circuits is to build the
transistors using small-bandgap semiconductors.
In a control experiment [6], Dill et al. showed that Ge
bipolar circuits could be three times faster than Si bipolar
circuits because of the much higher electron and hole
mobilities in Ge. This, together with the merits of SOl lateral
bipolar transistors mentioned above suggests that symmetric
Fig. I. (a) Schematic illustrating the structure of an SOl lateral NPN bipolar
transistor with symmetric emitter and collector regions. The quasi-neutral base
width Ws is narrower than the physical E-C separation by the depletion layers
from both E and C sides (After [2]). (b) Outline of CMOS-like process flow
used for Ge-Ol device fabrication.
lateral Ge-on-insulator (Ge-Ol) bipolar transistors could be an
excltmg, scalable, high-performance, and low-power
technology. In this paper, we report the first demonstration of
Ge-Ol symmetric lateral NPN transistors, built using a
fabrication process sequence similar to those used previously
and successfully to fabricate Si-OI and SiGe-OI transistors [4,
5]. The measured Ge-Ol device currents are compared with
those from the Si-OI and SiGe-OI devices, and examined to
shed light on process-related device physics.
II. DEVICE FABRlCATlON
Figure l(a) shows a schematic cross section an SOl lateral
NPN transistor. The Ge-Ol transistors were fabricated using a
CMOS-like process similar to those used to fabricate Si-OI
and SiGe-OI lateral transistors [4, 5]. The process flow is as
illustrated in Fig. l(b). The 8-inch Ge-OI wafers were
supplied by Soitec and were formed by wafer bonding
technique. A standard 90nm CMOS mask set was used for
device fabrication, resulting in a patterned physical gate length
(LG) of about 60nm with a mask dimension (LOES) of 80nm.
After the gate is patterned (extrinsic base poly SiGe layer), a
thin (1 nm) layer of AhO} is deposited by ALD on the
exposed Ge surface to passivate the Ge surface [7].
Subsequently, a 55-nm composite dielectric of Si02 and SiNx
was added before the vertical spacer (spacer 1) was formed by
RIE. It should be noted that while the Ge surface under the
spacer is passivated by AhO}, the Ge surface at the BOX is
not. As fabricated, the Ge-Ol wafers have Ge in contact with

978-1-5090-0484-3/16/$31.00 ©2016 IEEE 130

 18=1 /lA//lm to 10 /lA//lm
(a) Ge:N,=1E19As
t ....
2001 �
SiGe:N,=4E20 As ...
.
10� Si:N�=4E20 AS--,""+---� I
E:::l
<c
20 100 I
� 10-71 "'c'v'� "'1",c'v7L . I
�:d-----I
--'" ....<:>
..

10-9f--f I-/- f I I
O� 1
0.5 1.0 10-11 g rItC') Al .... \l\.!l��,!
VCE(V) 1.0
Fig. 2. Measured output characteristics for a typical Ge-Ol NPN bipolar
transistor. The device has emitter length LE O.2/lm.
=
(b) Ge:N,=1E19AS
l
SiGe:N,=4E20 As
10.5 Si:N�=4E20 As I � :bY
silicon dioxide at the BOX interface.
Devices with arsenic doped and phosphorous doped E/C � 10-71 ---p. I �;L
�.�
�

regions were both fabricated on the same wafer using masked ....OJ
..
ion implantation. The E/C doping concentration is relatively
3 10.91J( I 7/
low, only lxlOl9 cm- , being limited by the low n-type dopant
/
solubility in Ge. The data shown hereafter are for Ge-OI
10-" I lIIh t/\�""'Al' "I /,'
devices with arsenic doped E/C regions unless stated o 0.5 1.0

otherwise. VBE(V)
Fig. 3. (a) Gummel plots for lateral Ge-Ol NPN bipolar transistor with NE =

III. EXPERIMENTAL DATA AND DISCUSSION I x 1019 cm-3 by implantation. Also plotted are the data for lateral Si-OI and
SiGe-OI NPN devices, both with NE 4xl02o cm-3 by implantation. All three
=

Fig. 2 shows the measured output characteristics of a
typical Ge-OI NPN lateral bipolar transistor. The large series
resistance is mainly due to the relatively lightly doped E/C
regions and partly to the fact that no gennanide was formed on
the doped regions. The collector current Ie is determined by
the intrinsic-base region design, and the base current ls is a
function of the emitter-region design as well as a function of
"recombination defects" in the emitter-base diode space­
charge region. Judging from the current ratio Iells in Fig. 2, a
maximum current gain of greater than 20 should be achievable
even at small VBE if the various base current components (see
next subsection) could be suppressed. These current
components are discussed further below.
A. Collector current and base-region energy bandgap
The Gummel plots shown in Fig. 3(a) demonstrate that a
Ge-Ol device can achieve the same Ie as a Si-Ol device but at
� 460 mV lower VBE. Also plotted in Fig. 3 is the data of a
SiGe-OI device from [5], which shows the same Ie as the Si-
IB(V�E)
devices have about the same WE. Ge-Ol device shows the same Ie at 460 mV
lower VEE (l30mV for SiGe-OI device) than Si-Ol device. The dashed line for
the Ge-Ol device is the projected current if the device emitter series resistance
were negligible. (b) Base currents of the same devices shown in (a).
B. Base current components
Fig. 3(b) shows that the Ge-OI device exhibits much higher
'non-ideal' base current (slope > 60 mY/decade) than the Si­
OI and SiGe-OI counterparts. To explore how to reduce IB in
Ge-OI lateral bipolar devices in order to achieve higher
current gain, we take a closer look at the base current
components in the Ge-Ol bipolar device. To this end, we
follow the same methodology previously employed to gain
insight into the base current of Si-OI and SiGe-OI devices [8].
The base current in an SOl lateral bipolar transistor has three
components as described by Eq. (1) and also illustrated in Fig.
4 for an NPN transistor:
=

01 device but at about 130 mV lower VBE• These results

(JBo,inj + IBo,ree) exp(V�dkT) +
confirm the scaling of operation voltage VBE with IBo.seexp (qV�d2kT) , (1)
semiconductor bandgap in the base. with
2
In Fig. 3(a), the Ge device shows Ie saturating at a much
qDpEni
IBO,inj NEW
eE
'
lower value than the SiGe and Si devices due to its much qWBn eB [
larger emitter series resistance compared to the SiGe and Si IBO,ree =
2TnBNB '

devices. The Ge device has relatively low emitter doping

IBo.se
qniWdBE

concentration (NE 1x1019 cm, ) compared to the SiGe and Si

3 =
T n.sC+Tp,5C
'
=

devices (NE 4x10 cm, ). In addition, there is no gennanide

20 3
=

fonned on its E/C regions of the Ge device, while the SiGe

and Si devices have silicide formed on their E/C regions.

131

WdBE
Fig. 4. Base current components in the lateral bipolar transistor.
where TnB is the minority electron lifetime in the quasineutral
base region and Tn,Se and Tp,se are the recombination lifetimes
for electrons and holes, respectively, in the E-B diode space­
charge region. In Eq. (1), JB,lnj is the injection component due
to injection of holes from the base into the emitter, JB,rec is the
base recombination current from the recombination in the
quasineutral base region, and JB,se is base current due to
recombination in the E-B diode space-charge region.
Auger recombination dominates minority-carrier lifetime in
the quasineutral base. The Auger recombination coefficient in
31
p-type Ge is about 10- cm% [9], approximately the same as
in p-type Si [10]. Therefore, just like for a Si-OI NPN, we
expect the base current component JB,rec due to recombination
in the quasineutral base to be small compared to the other two
components for a Ge-Ol NPN devices as well.
According to Eq. (1), both JB,jnj and JB,rec have an 'ideal'
slope of 60 mY/decade as a function of VBE while JB,se has a
slope of 120 mV/decade. Following the methodology
described in [8], we deduce the 'ideal' base current in our Ge-
01 devices by dividing the measured collector current by the
peak or flat part of the measured current gain (Ie/IB). With
JB,rec being negligible, this "ideal" (lB_60mV/dec) base current
is due to JB,inj alone. This ideal base current component for the
Ge-OI device in Fig. 3 is shown in Fig. 5. After E/C implant,
this device was processed with rapid thennal anneal (RTA) at
575°C and twice at 600°C. In Fig. 5, the ls_60mV/dec
component deduced from the measured IB after each annealing
step is shown. The data suggest relatively little change after
the additional 600°C anneal, suggesting the implanted E/C
regions were likely adequately annealed even at 575°C.
Once the 60mV/decade base current component has been
E � lO'8L. �����I----- I;
::t
::c 10'8l
U
-/':-
.#-+I-----j
OJ
3 E
E o
o N
"'I
...."'10'9 ���
/--1I------+----J
0.18 0.24 0.30
VSE(V)
Fig. 5. The "Ideal" base current component of the Ge-Ol BJT devices after
several cycles of RTA at different temperatures.
132
determined, the 120mV/decade component can be obtained by
simply subtracting the 60mV/decade component from the
measured base current. Fig. 6 shows the 120mV/dec
components of base current of the devices in Fig. 3. The
IB_120mV/dec component of the Ge-OI device shows slight
decrease with additional RTA, suggesting slight reduction of
recombination in the E-B diode space-charge region. The
ls_120mV/dec component of the Si-OI and SiGe-OI devices
are also plotted in Fig. 6 for comparison. Compared to the Si-
01 device, the SiGe-OI device shows about a factor of 100
larger current and the Ge-Ol device shows about a factor of
106 larger current. As indicated by the JBo,se term in Eq. (1),
the larger IB_120mV/dec component is due to two factors: (i)
larger intrinsic carrier density nj, and (ii) increased
recombination in the E-B diode space-charge region.
For the case of comparing the SiGe-OI device with the Si-
01 device [8], it was shown that a factor of �13x could be
attributed to the n, factor (due to the SiGe device having a
base bandgap about 130 meV smaller than the Si device, as
suggested by the measured collector current) and a factor of
�8x could be attributed to increased recombination caused by
residue defects from E/C implant damages.
For the case of comparing the Ge-OI device with the Si-OI
device, the n, factor is �2000 (ratio of nj for Ge to n, for Si),
suggesting a factor of �500 due to increased recombination in
the E-C diode space-charge region. This large increase in
recombination could have one or more of the following
components: (i) recombination defects caused by residual E/C
implant damage, (ii) larger recombination volume (the
parameter WdBE in the JBo,se term), and (iii) larger
recombination at the Ge/spacer interface and/or the Ge/BOX
interface. The emitter doping level of the Ge-OI device is only
3
lx1019 cm- , much lower than that for the Si-OI and SiGe-OI
devices, suggesting that there should not be significant
residual defects from E/C implant damage in the Ge-OI device.
The lower NE for the Ge-OI device, however, does imply a
larger WdBE value, by about a factor of 2, for the Ge-Ol device
than for the SiGe-OI and Si-OI devices. The net is that the
very large increase of the recombination base current in the
Ge-OI device is likely due to recombination at the Ge/spacer
and/or the GelBOX interface.
lO'6k
[:�l�:==F====F==--
JI'F
::c
'g'
"0
:> 10,'0
�2nd600C -+��_�__�
__
)O"2� J
1
0.24 0.48 0.72
VSE(V)
Fig. 6. Base current component due to recombination in the E-B diode space­
charge region for the Ge-Ol, SiGe-OI, and SOl BJT devices in Fig. 3. The
dashed line has a slope of 120mV/decade.
 (a)
10·'
1�� ��--�---+--�II I
ElO·6
E
� 10·7 I
:::l .
�<F :h
� 0-7
8?" _
' I I _°::.1
--'" -"10.8

VCB=OV 10·'
o 0.12 0.24 0.36 0.48 0.60
& l !""v i I VSE(V)
10-11
0.1 0.3 0.5 0.7
VSE(V)
Fig. 7. Gummel plots comparing lateral Ge-Ol bipolar transistors with E/C
(b�o·,
regions doped by arsenic or phosphorous implantation. The arsenic device 1�
shows about 2x higher collector current than the phosphorus device. E1�
� 1�
As noted in Section II, the Ge/spacer interface is passivated �1�
with Ab03, but the Ge/BOX interface is not passivated. �1�
Therefore, it is likely the observed large ls_120mV/dec base 10�
current component in the Ge-OI device is due to 0.48 0.72 0.96 1.20
recombination at the Ge/BOX interface within the E-B diode VBE(V)
space-charge region. This conclusion suggests the need to Fig. 8. Gummel current characteristics measured at fixed VCE for (a) Ge-Ol
device and (b) SiGe-OI and SOl devices.
passivate the Ge/BOX interface in the development of Ge-OI
substrate technology.
C. EIC regions doped with implanted arsenic or phosphorus OI substrate technology with passivated Ge/BOX interface
Devices with arsenic doped and phosphorous doped E/C must be fust developed.
regions were both fabricated on the same wafer using masked ACKNOWLEDGMENT
ion implantation. Fig. 7 shows the measured collector and
base currents in the two devices. The device with arsenic The authors would like to thank Dr. Effendi Leobandung
doped E/C regions shows higher collector current than the for technical discussions and management support. We also
device with phosphorus doped E/C regions because of the thank Soitec for providing the Ge-OI wafers and
faster diffusion of arsenic, resulting in smaller Ws and hence Microelectronics Research Laboratory at IBM T. J. Watson
larger collector current. Research Center for device fabrication.

D. Collector-base reverse-bias diode leakage current REFERENCES

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characteristics of the Si-OI and SiGe-OI devices at fixed VeE
of 0.9 V are shown in Fig. 8(b) for comparison. The Si-OI
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diode leakage which is consistent with the very small
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IV. CONCLUSION
We report the fust demonstration of Ge-OI lateral bipolar
transistors, fabricated using a CMOS-compatible process flow.
This novel bipolar device presents exciting opportunities for
low voltage and high performance bipolar circuits. However,
in order to realize the potential of this novel technology, Ge-
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