Unit-V-Introduction To AVR RISC PDF

Department of Electronics and
Telecommunications
Introduction to AVR RISC

Microcontroller Architecture
(Unit V)
Instructor
Dr. Yogesh H. Dandawate , Prof. Pravin G.Gawande and
Prof.Rahul S.Pol
Department of Electronics and Telecommunications (C005)
Vishwakarma Institute of Information Technology,Pune
Email : yogesh.dandawate@viit.ac.in
Unit-V-Introduction to AVR RISC Microcontroller

1
Architecture
Unit V : Department of Electronics
Introduction to AVR RISC and Telecommunications
Microcontroller Architecture
• Overview of AVR family, AVR Microcontroller architecture
• Introduction To 8-bit AVR Microcontroller, AVR register,
ROM space and other hardware modules, ATmega32 pin
configuration & function of each pin
• Addressing modes of AVR, Data transfer Arithmetic, Logic
and Compare, Rotate and Shift, Branch and Call
instructions. AVR data types and assembler directives,
AVR assembly language programs.

2
Architecture
Features of Reduced Instruction Department of Electronics
Set Computers (RISC) and Telecommunications
• Reduced Instruction set size and less complex

instructions.
• Fixed length instructions
• Limited loading and storing instructions, memory access.
• Fewer addressing modes
• Instruction pipeline.
• Large no.of registers.
• Hardwired control unit.
• Delayed loads and branches.

3
Architecture
RISC Features contd..
Department of Electronics
and Telecommunications
• Speculative execution of instructions.

• Optimizing Compiler.
• Separate Instructions and data streams.

4
Architecture
Features of AVR Department of Electronics
(General)
• RISC Architecture (Harvard) with mostly fixed length
instructions,load-store memory access
• Two stage (Multi) instruction pipeline that speeds up
execution.
• Majority instruction take one machine cycle.
• Up to 16 MHz clock operation.
• Internal Program and Data Memory. (On chip Flash )
• In system Programmable.
• Available in 8 pin to 64 pin package size to suit variety of
applications.
• Upto 10 to 12 times performance speed up over conventional
CISC controllers.
5
Architecture
• Wide variety of On-Chip Peripherals

1) Digital I/O
2) ADC
3) EEPROM
4) Timers (With Prescaler)
5) UART
6) RTC Timer
7) PWM
8) Watch Dog Timer (WDT)
6
Architecture
• Wide operating voltages from 2.7 to 6.0 V.

• 32 bytes general purpose working registers.
• Internal and External Interrupt sources.
• Sleep and POWER DOWN modes of Operation.

7
Architecture
AVR series of Department of Electronics
Microcontrollers (History)
• AT 90S1200- 20Pins-16MHz-1K
• AT 90S2312-20-10-2K-128RAM-UART
• AT90S2323-8-10-2K-128
• AT 90S2343 -8-10-2K
• AT 90S2333-28-10-2K-128RAM-UART-ADC
• AT 90S4433-28-10-4K-128RAM-UART-ADC
• AT 90S4414-40-10-4K-256RAM-UART
• AT 90S4434-40-10-4K-256RAM-UART-ADC

8
Architecture
AVR series of Microcontrollers Department of Electronics
(In Demand-Last Decade )
• Mega 103-64-6-128K-4KRAM-UART-ADC
• Mega 603
• Tiny 10- 8- 10-1K
• Tiny 12
• Mega 8
• ATMega 16
• ATMega 32

9
Architecture
AVR Microcontrollers Department of Electronics
Now
• AT tiny
• Atmega (ATmega 32)
• Atxmega
• Visit
• https://www.microchip.com/design-centers/8-bit/avr-mcus
10
Architecture

11
Architecture
Source : www.microchip.com

12
Architecture
Atmel Microcontrollers

13
Architecture
Features of ATmega32
• High-performance, Low-power Atmel®AVR® 8-bit

Microcontroller
• Advanced RISC Architecture
• 131 Powerful Instructions – Most Single-clock Cycle
Execution
• 32 × 8 General Purpose Working Registers
• Fully Static Operation
• Up to 16 MIPS Throughput at 16MHz
• On-chip 2-cycle Multiplier

14
Architecture
• High Endurance Non-volatile Memory segments

• 32Kbytes of In-System Self-programmable Flash program
memory
• 1024Bytes EEPROM
• 2Kbytes Internal SRAM
• Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
• Data retention: 20 years at 85°C/100 years at 25°C(1)
• Optional Boot Code Section with Independent Lock Bits
• In-System Programming by On-chip Boot Program
• True Read-While-Write Operation
• Programming Lock for Software Security
15
Architecture
• JTAG (IEEE std. 1149.1 Compliant) Interface

• Boundary-scan Capabilities According to the JTAG Standard
• Extensive On-chip Debug Support
• Programming of Flash, EEPROM, Fuses, and Lock Bits through
the JTAG Interface.
• I/O and Packages
• 32 Programmable I/O Lines
• 40-pin PDIP, 44-lead TQFP, and 44-pad QFN/MLF
• Operating Voltages
• 2.7V - 5.5V for ATmega32L
• 4.5V - 5.5V for ATmega32

16
Architecture
• Peripheral Features
• Two 8-bit Timer/Counters with Separate Prescalers and Compare
Modes
• One 16-bit Timer/Counter with Separate Prescaler, Compare Mode,
and Capture Mode
• Real Time Counter with Separate Oscillator
• Four PWM Channels
• 8-channel, 10-bit ADC
• 8 Single-ended Channels
• 7 Differential Channels in TQFP Package Only
• 2 Differential Channels with Programmable Gain at 1x, 10x, or 200x
• Byte-oriented Two-wire Serial Interface
• Programmable Serial USART
• Master/Slave SPI Serial Interface
• Programmable Watchdog Timer with Separate On-chip Oscillator
• On-chip Analog Comparator

17
Architecture
• Special Microcontroller Features

• Power-on Reset and Programmable Brown-out Detection
• Internal Calibrated RC Oscillator
• External and Internal Interrupt Sources
• Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down,
Standby and Extended Standby.
• Speed Grades
• 0 - 8MHz for ATmega32L
• 0 - 16MHz for ATmega32
• Power Consumption at 1MHz, 3V, 25°C
• Active: 1.1mA
• Idle Mode: 0.35mA
• Power-down Mode: < 1μA

18
Architecture
AVR CPU Core

19
Architecture
ATmega32 datasheet Architecture
20
ATmega32
21
Pin Diagram
Used as
bidirectional I/O
port and 8
channel ADC
22
Port B
• Bidirectional I/O as well as alternate functions.

Pin Alternate Function Description
PB7 SCK (SPI Bus Serial Clock)
PB6 MISO (SPI Bus Master Input/Slave Output)
PB5 MOSI (SPI Bus Master Output/Slave Input)
PB4 SS (SPI Slave Select Input)
PB3 AIN1 (Analog Comparator Negative Input)
OC0 (Timer/Counter0 Output Compare Match Output)
PB2 AIN0 (Analog Comparator Positive Input)
INT2 (External Interrupt 2 Input)
PB1 T1 (Timer/Counter1 External Counter Input)
PB0 T0 (Timer/Counter0 External Counter Input)
XCK (USART External Clock Input/Output)
23
Architecture
Port C
• Bidirectional I/O as well as alternate functions.

PC7 TOSC2 (Timer Oscillator Pin 2)
PC6 TOSC1 (Timer Oscillator Pin 1)
PC5 TDI (JTAG Test Data In)
PC4 TDO (JTAG Test Data Out)
PC3 TMS (JTAG Test Mode Select)
PC2 TCK (JTAG Test Clock)
PC1 SDA (Two-wire Serial Bus Data Input/Output Line)
PC0 SCL (Two-wire Serial Bus Clock Line)

24
Architecture
Port D

PD7 OC2 (Timer/Counter2 Output Compare Match Output)
PD6 ICP1 (Timer/Counter1 Input Capture Pin)
PD5 OC1A (Timer/Counter1 Output Compare A Match Output)
PD4 OC1B (Timer/Counter1 Output Compare B Match Output)
PD3 INT1 (External Interrupt 1 Input)
PD2 INT0 (External Interrupt 0 Input)
PD1 TXD (USART Output Pin)
PD0 RXD (USART Input Pin)

25
Architecture
AVR Family Architecture
• POINTS TO REMEMBER
 Program memory 16 bit wide.
Program memory also stores interrupt Vectors.
 Data Memory is divided into
a) Reg.File with 32 reg.of 8 bit each.
b) 64 I/O reg.of 8 bit (some have more)
c) Stack Pointer 8 bit, some times 16 bit.
(If no SRAM then internal 3 locations serve as SP)
d) External SRAM
26
Architecture
e) On chip EEPROM accessed in separate memory

map.
f) Most AVR instructions are 1 word long so take 1
program memory location.

27
Architecture
Memory Map
Program Memory Data Memory Data EEPROM
0000
0000
32
Reg.File
$1F
$20 $ 00
64 I/O Reg.
$ 5F $ 3F
16 Bits Internal 8
SRAM
November 5, 2020 Y.H.Dandawate 28

The Register File
00 R0
R1
0F
R16
R26
X Register Low Byte
R27
X Register High Byte
R28
Y Register
R29
R30
Z Register
1F R31

Different Registers
• Status
• Stack Pointer Note : The number of register may change
Depending upon the chip specifications
• Interrupt -- 2 nos.
• MCU --- 2 nos
• Timer --- 7 nos ( For 2 timers)
• Watch Dog Timer --- 1 no.
• EEPROM ---- 3 nos
• Port B --- 3 nos
• Port D --- 3 nos
• SPI – 3 nos
• UART – 4 nos
• Analog Comparator --- 1 no

Status Register (SREG)
7 6 5 4 3 2 1 0
I T H S V N Z C
I -- Global Interrupt Enable

T – Bit copy Storage (BLD (Bit LoaD) and BST (Bit STore) use the T-
bit as source or destination)
H – Half Carry
S: Sign Bit, S = N ⊕ V V: Two’s Complement Overflow Flag
N: Negative Flag
I/O address is $3F H and after reset it is 00

Stack Pointer (Facts)
• 1 Byte wide for 256 bytes of SRAM.

• 2 Bytes wide for more than 256 bytes.
• After reset initialized to 00 or 0000h.
• To be initialized before used. (Normally after $60)
• SP decrements after Push.

Instruction Department of Electronics
Execution Timing Source : www.microchip.com
ATmega32 datasheet
• Parallel Execution

33
Architecture
Single Cycle ALU Department of Electronics
Operation Source : www.microchip.com
ATmega32 datasheet

34
Architecture
ATmega 32 Memories
Program Memory
H.W
Unit-V-Introduction to AVR EEPROM
RISC 1 K memory
Microcontroller
ATmega32 datasheet 35
EEAR ,EECR and EEDR register
Architecture
ATmega 32 Clock Department of Electronics
Distribution
Source :
www.microchip.com
ATmega32 datasheet

36
Architecture
Timer/Counter 0 with Department of Electronics
PWM
• Single Compare Unit Counter
• Clear Timer on Compare Match (Auto Reload)
• Glitch-free, Phase Correct Pulse Width Modulator (PWM)
• Frequency Generator
• External Event Counter
• 10-bit Clock Prescaler
• Overflow and Compare Match Interrupt Sources (TOV0
and OCF0)

37
Architecture
Timer/Counter 0 with Department of Electronics
PWM
ATmega32 datasheet
38
Architecture
16-bit Department of Electronics
Timer/Counter1
• True 16-bit Design (that is, allows 16-bit PWM)
• Two Independent Output Compare Units
• Double Buffered Output Compare Registers
• One Input Capture Unit
• Input Capture Noise Canceler
• Clear Timer on Compare Match (Auto Reload)
• Glitch-free, Phase Correct Pulse Width Modulator (PWM)
• Variable PWM Period
• Frequency Generator
• External Event Counter
• Four Independent Interrupt Sources (TOV1, OCF1A, OCF1B, and ICF1)

39
Architecture
16-bit Department of Electronics
Timer/Counter1
H.W : Timer /Counter 2 Unit-V-Introduction to AVR RISC Microcontroller ATmega32 datasheet40
Architecture
Serial Peripheral Department of Electronics
Interface – SPI
• Full-duplex, Three-wire Synchronous Data Transfer
• Master or Slave Operation
• LSB First or MSB First Data Transfer
• Seven Programmable Bit Rates
• End of Transmission Interrupt Flag
• Write Collision Flag Protection
• Wake-up from Idle Mode
• Double Speed (CK/2) Master SPI Mode

41
Architecture
Serial Peripheral Department of Electronics
Interface – SPI
ATmega32 datasheet
42
Architecture
USART
• Full Duplex Operation (Independent Serial Receive and Transmit Registers)

• Asynchronous or Synchronous Operation
• Master or Slave Clocked Synchronous Operation
• High Resolution Baud Rate Generator
• Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits
• Odd or Even Parity Generation and Parity Check Supported by Hardware
• Data OverRun Detection
• Framing Error Detection
• Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter
• Three Separate Interrupts on TX Complete, TX Data Register Empty, and RX
Complete
• Multi-processor Communication Mode
• Double Speed Asynchronous Communication
Unit-V-Introduction Mode
to AVR RISC Microcontroller
43
Architecture

44
Architecture
• Calculating Baud rate

45
Architecture
Two wire Serial Department of Electronics
Interface (I2C)
• Simple Yet Powerful and Flexible Communication Interface, Only
Two Bus Lines Needed
• Both Master and Slave Operation Supported
• Device Can Operate as Transmitter or Receiver
• 7-bit Address Space allows up to 128 Different Slave Addresses
• Multi-master Arbitration Support
• Up to 400kHz Data Transfer Speed
• Slew-rate Limited Output Drivers
• Noise Suppression Circuitry Rejects Spikes on Bus Lines
• Fully Programmable Slave Address with General Call Support
• Address Recognition causes Wake-up when AVR is in Sleep Mode
46
Architecture

47
Architecture
Analog Comparator
ATmega32 datasheet

48
Architecture
Analog to Digital
Converter
• 10-bit Resolution
• 0.5 LSB Integral Non-linearity
• ±2 LSB Absolute Accuracy • 0 - VCC ADC Input Voltage
• 13 μs - 260 μs Conversion Time Range
• Up to 15 kSPS at Maximum • Selectable 2.56V ADC
Resolution Reference Voltage
• 8 Multiplexed Single Ended Input • Free Running or Single
Channels Conversion Mode
• 7 Differential Input Channels • ADC Start Conversion by Auto
• 2 Differential Input Channels with Triggering on Interrupt Sources
Optional Gain of 10x and 200x
• Interrupt on ADC Conversion
• Optional Left adjustment for ADC Complete
Result Readout
• Sleep Mode Noise Canceler
49
Architecture
50
Architecture
Home Work
• Interrupt and Interrupt Vector Locations

• Register Summary

51
Architecture
Programming AVR
Instruction Set

52
Architecture
Addressing Modes
1) Register Direct ( Single Register)

Ex. INC Rd , CLR Rd
2) Register Direct ( Two registers)
Ex. ADD Rd,Rs
3) I/O Direct
Ex. IN Rd,Port Add
4) Data Direct
Ex. LDS Rd,16 bit add

53
Architecture
Addressing Modes
5) Data Indirect : Uses Pointer register (X,Y or Z) The base

address is stored and offset specified in the instruction is
added or some increment/decrement operations are also
performed . LD Rd,X+
6) Indirect Program Addressing
Z register is used to point to the program
Memory.Specially used with JMP instructions.
7) Relative Program Addressing :Offset of 2 K is Used

54
Architecture
Categories of Department of Electronics
Instruction Set
• Data Transfer
• Arithmetic Instructions.
• Logical Instructions.
• Program Control Instructions.
• Bit and Bit Test Instructions.
• H.W Summary Sheet of AVR

55
Architecture
Reference
• Datasheet of AVR
• Chapter 1-4 , Programming and Customizing AVR
microcontroller, by Dhananjay Gadre

56
Architecture
Questions???
Thank You

57
Architecture

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Department of Electronics and

Introduction to AVR RISC

Unit-V-Introduction to AVR RISC Microcontroller

Unit-V-Introduction to AVR RISC Microcontroller

• Reduced Instruction set size and less complex

Unit-V-Introduction to AVR RISC Microcontroller

• Speculative execution of instructions.

Unit-V-Introduction to AVR RISC Microcontroller

• Wide variety of On-Chip Peripherals

• Wide operating voltages from 2.7 to 6.0 V.

Unit-V-Introduction to AVR RISC Microcontroller

Unit-V-Introduction to AVR RISC Microcontroller

Unit-V-Introduction to AVR RISC Microcontroller

Unit-V-Introduction to AVR RISC Microcontroller

Unit-V-Introduction to AVR RISC Microcontroller

Unit-V-Introduction to AVR RISC Microcontroller

• High-performance, Low-power Atmel®AVR® 8-bit

Unit-V-Introduction to AVR RISC Microcontroller

• High Endurance Non-volatile Memory segments

• JTAG (IEEE std. 1149.1 Compliant) Interface

Unit-V-Introduction to AVR RISC Microcontroller

Unit-V-Introduction to AVR RISC Microcontroller

• Special Microcontroller Features

Unit-V-Introduction to AVR RISC Microcontroller

Unit-V-Introduction to AVR RISC Microcontroller

• Bidirectional I/O as well as alternate functions.

• Bidirectional I/O as well as alternate functions.

Unit-V-Introduction to AVR RISC Microcontroller

Pin Alternate Function Description

Unit-V-Introduction to AVR RISC Microcontroller

e) On chip EEPROM accessed in separate memory

Unit-V-Introduction to AVR RISC Microcontroller

Program Memory Data Memory Data EEPROM

November 5, 2020 Y.H.Dandawate 28

November 5, 2020 Y.H.Dandawate 29

November 5, 2020 Y.H.Dandawate 30

I -- Global Interrupt Enable

November 5, 2020 Y.H.Dandawate 31

• 1 Byte wide for 256 bytes of SRAM.

November 5, 2020 Y.H.Dandawate 32

Unit-V-Introduction to AVR RISC Microcontroller

Unit-V-Introduction to AVR RISC Microcontroller

Unit-V-Introduction to AVR RISC Microcontroller

Unit-V-Introduction to AVR RISC Microcontroller

Unit-V-Introduction to AVR RISC Microcontroller

Unit-V-Introduction to AVR RISC Microcontroller

• Full Duplex Operation (Independent Serial Receive and Transmit Registers)

Unit-V-Introduction to AVR RISC Microcontroller

• Calculating Baud rate

Unit-V-Introduction to AVR RISC Microcontroller

Unit-V-Introduction to AVR RISC Microcontroller

Unit-V-Introduction to AVR RISC Microcontroller

• Interrupt and Interrupt Vector Locations

Unit-V-Introduction to AVR RISC Microcontroller

Unit-V-Introduction to AVR RISC Microcontroller

1) Register Direct ( Single Register)

Unit-V-Introduction to AVR RISC Microcontroller

5) Data Indirect : Uses Pointer register (X,Y or Z) The base

Unit-V-Introduction to AVR RISC Microcontroller

• H.W Summary Sheet of AVR

Unit-V-Introduction to AVR RISC Microcontroller

Unit-V-Introduction to AVR RISC Microcontroller

Unit-V-Introduction to AVR RISC Microcontroller