6.3 Decoder: A decoder is @ logic circuit which has a set of inputs representing a binary number and gives only one output comesponding fo the input mumbes. The decoder activates one output at a time depending upon the input binary number; all other outputs, will be inactive. Figure 6.12 shows the functional block diagram of a decoder having N’ inputs and K ourputs, The possible combinations of V inputs will be 2" = X, so there will be K ouputs, tb i Winpute Tp Xz K Outputs hea Keer Figure 6.13 shows the circuit diagram of 3 — to ~ 8 line decoder. It will have three input lines and 2° = 8 output lines, When the three bit binary number is fed to the input of the decoder, as discussed above one output line corresponding to input binary is activated and all other output lines will be inactive. It is also called binary to octal decoder or converter because it takes a binary code as input and activates one of the eight (octal) ‘output lines corresponding to the input binary code, The 3 — to — 8 can also be referred to as a1 —of ~8 line decoder. because only one of the eight outputs is activated at a time. ‘The truth table for 3 — to —§ line decoder is shown in table 6.6. 4 cE Gnabie) Fig. 6.13 Table 6.6 iat Eee Carpate ABC E|D; De Ds Ds Da Dp Di Do gee [00000 000 000 1/00 0000014 oo1 1fo0 000010 o10 1/00 000100 o11 1fo0 001 000 too t]00 0160000 101 1/00 100000 110 1/01 0060 000 Lii_ijt1o0 000 000Jip cleat foun the Gwe 6.13 dhat aut Enable input line iy coumceted to dhe fount input of each gate, When the Enable input is connected to logic 0, all the gates will be disabled and force all output to be zero irrespective of the input data (ABC). However. the decoder will give the required data when the Enable terminal is held at logic 1. The functional block diagram of 3 8 line decoder is shown in figure 6.14. Dy Dy PRLPSY. E Gnable) Fig. 6.14 ‘The 4:16 line decoder can also be explained on the same pattem. It may be mentioned here that if AND are used in designing the decoder circuit. then Enable and all outputs will be active high. If on the other hand the decoder circuit is designed using AND gates then the Enable as well as the outputs terminals will be active low. Further it is interesting to note that the decoder can function as a demultiplexer For example a 2:4 line decoder with Enable terminal cau be used as a 1:4 DMUX. if the Enable terminal E is used as the data input tine for the DMUX and the two input A & B of the decoder as the select terminals for the DMUX. Iti illustrated in figure 6.15. lo. a 4 ia Loe EGeabl) |g DE Decoder $ ata —| 3 2 Be input | PMO -— Ps B Dad -—Bo ' I E Enable) Ag. Select terminals Fig. 6.15 Decoder/Demultiplexer circuits can be expanded to form the larger decoder circuit, For example two 3:8 line decoders with Enable terminal can be connected to form 416 line decoder. Figure 6..6 shows the construction of a 4:16 line decoder with two 3:8 line decoders. From this figure it is clear that when the enable terminal E 1s 0. decoder (1) is enabled and decoder (2) is disabled. The decoder (1), therefore, gives the outputs as per the value of ABC. When the enable terminal E is 1, decoder (1) 1s disabledand decoder (2) is enabled, The decoder (2) now gives the output as the input values. Here E terminal works as the most significant bit and C as the least significant bit. So EABC generates the binary input 0000 through 1111 De Dy Fig. 616 ‘The Boolean functions given in standard SOP form can be realized using the decoder circuits. For the realization of Boolean expressions, the decoder requires some gates also, The use of decoder for the implementation is more economical, as number of Boolean expressions can be implemented using one decoder and a few gates. However. in ‘multiplexers one MUX is used for one Boolean function,