TEM2P2EST: A Thermal Enabled Multi-model

Power/Performance ESTimator

1 2,3 2 3
Ashutosh Dhodapkar , Chee How Lim , George Cai , and W. Robert Daasch
1
Dept. of Electrical and Computer Engineering
University of Wisconsin-Madison
2
Intel Corporation
3
Dept. of Electrical and Computer Engineering
Portland State University

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Abstract. We present TEM P EST, a flexible, cycle-accurate micro-
architectural power/performance analysis tool based on SimpleScalar. The goal
was to build a “flexible” simulation tool, incorporating several estimation
models and providing a scalable framework for future development. This
approach is based on the fact that different power models have different
tradeoffs in terms of power estimation accuracy and flexibility/scalability. The
simulator generates power estimates based on either empirical data or analytical
models. In future, other modes like estimation based on RTL extraction can be
included. The tool includes analytical models for dynamic and leakage power,
di/dt power, dual Vt support and process technology scaling options. It has a
thermal model built to study thermal issues and techniques like clock throttling.
Initial studies show that our results are consistent and match well with real
design simulated with SPICE. In addition, we validated our temperature model
with measurement on a typical microprocessor heat solution.

1 Introduction

The last decade has seen a tremendous increase in microprocessor complexity, with
designers trying to squeeze every last bit of improvement in performance. This has
led to an inefficient use of transistors leading to high power dissipations [1]. Power
dissipation has become a significant issue in modern microprocessor design. In fact, it
has become one of the primary design constraints along with clock frequency and die
size [2]. In the mobile processor segment, increased power dissipation leads to
decreased battery life and hence can jeopardize the marketability of the product. In
case of high performance microprocessors, high power dissipation leads to thermal
issues like device degradation and reduced chip lifetime. To prevent overheating,
expensive heat sinks and packages are used, which add to the cost of manufacturing.
Present day microprocessors are already approaching ~100W total dissipated power
[3].

Power dissipation optimizations have mainly targeted dynamic or switching power as

it represents around 90% of the total dissipated power. However, people have now
started looking at leakage power, which is becoming increasingly important with
every process technology generation [4]. There has been some work on short-circuit

B. Falsafi and T.N. Vijaykumar (Eds.): PACS 2000, LNCS 2008, pp. 112-125, 2001.
© Springer-Verlag Berlin Heidelberg 2001
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TEM P EST: A Thermal Enabled Multi-model Power/Performance ESTimator 113

power dissipation, but this forms a negligible fraction in well-designed circuits [5].
Traditionally, power dissipation issues have been tackled at the process/circuit level.
However, over the last few years, it has become quite evident that “power aware”
micro-architecture definition can go a long way in reducing the power dissipation.
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In this paper, we present TEM P EST, a cycle-accurate, flexible and scalable tool for
power/performance analysis, based on SimpleScalar [6]. It supports simulation in the
empirical mode (using real design data) and the analytical mode (using analytical
models). It computes dynamic and static power, di/dt power, thermal statistics and has
several features, which are described in subsequent sections. The simulator can be
used by micro-architects and compiler designers to study tradeoffs, and come up with
power-efficient architectures and compiling techniques.

The next section looks at some prior work and motivation behind developing this
simulator. Section 3 describes the structure of the simulator. Section 4 describes the
power estimation modes, and Section 5 describes some preliminary validation results
and avenues of future development. Finally, Section 6 concludes the paper.

2 Motivation

Micro-architectural power estimation has been a hot field of research for the last few
years. Several micro-architectural power estimation methodologies have been studied.
These can be broadly classified into empirical methods and analytical methods [7]
and into fixed activity and activity sensitive methods[8]. Until recently, researchers
have predominantly focused on caches, due to their relatively large on-chip area and
their regular structure, that makes them easier to model [9], [10]. However, with the
significantly higher power dissipation in the data-path of modern out of order
superscalar processors [11], it makes sense to look at the whole chip rather than just
caches. The earliest effort in this direction was ESP [12], a power simulator based on
a simple five stage RISC pipeline. In the last couple of years, at least three significant
full chip micro-architectural power estimation tools have been unveiled [13], [14],
[15], both based on SimpleScalar. Our work is the extension of the Cai-Lim simulator
[13].

The Cai-Lim model and the Wattch [14] use different estimation methodologies. The
former uses a very detailed empirical model using power density data from real
design, while the latter uses analytical models. Though the Cai-Lim model is more
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detailed, it is difficult to scale to other technologies and designs. TEM P EST tries to
bridge this gap by providing an analytical mode in addition to the empirical mode.
Another goal was to have a highly flexible and scalable infrastructure which would be
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amenable to future development. In its present stage of development, TEM P EST
provides two different modes of simulation, which compute dynamic power, leakage
power and di/dt power. They have support for dual Vt technology and technology
scaling. The analytical models have several features like choice of dynamic and static
decoders, dual and single rail sensing and miller capacitance corrections. We have a
temperature model built into the simulator, which to our knowledge is done by no
other simulator. This model can be used to study thermal distribution and mechanisms
like clock throttling. The power estimation structure has been modularized and