Proceedings of the ASME 2013 International Technical Conference and Exhibition on
Packaging and Integration of Electronic and Photonic Microsystems
Experimental Measurement of the Thermal Performance of a Two-Die 3D
Integrated Circuit (3D IC)
Leila Choobineh
Mechanical and Aerospace Engineering
University of Texas, Arlington
Trent Uehling
Freescale Semiconductor
Austin, TX
ABSTRACT
Accurate measurement of the thermal performance of
vertically-stacked three-dimensional integrated circuits (3D
ICs) is critical for optimal design and performance.
Experimental measurements also help validate thermal models
for predicting the temperature field in a 3D IC. This paper
presents results from thermal measurements on a two-die 3D IC.
The experimental setup and procedure is described. Transient
and steady-state measurements are made while heating the top
die or the bottom die. Results indicate that passage of electrical
current through the heaters in top/bottom die induces a
measureable temperature rise. There appears to be a unique
asymmetry in thermal performance between the top die and the
bottom die. The top die is found to heat up faster and more than
the bottom die. Results presented in this paper are expected to
play a key role in validation of simulation-based and analytical
thermal models for 3D ICs, and lead to a better fundamental
understanding of heat transport in stacked systems. This is
expected to lead to effective thermal design and
characterization tools for 3D ICs.
Keywords: Three-dimensional integrated circuits (3D
ICs), thermal measurements, semiconductor devices, multi-die
stacked systems, thermal conduction.
1 Copyright © 2013 by ASME
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InterPACK2013
July 16-18, 2013, Burlingame, CA, USA
IPACK2013-73167
Nick Vo
Freescale Semiconductor
Austin, TX
Ankur Jain
Mechanical and Aerospace Engineering
University of Texas, Arlington
Email: jaina@uta.edu; Ph: (+1)-817-272-9338;
Web: www.uta.edu/mtl
1. INTRODUCTION
Thermal management of three-dimensional integrated circuits
(3D ICs) has attracted significant research interest in the recent
past [1-6] due to the promising electrical performance of
stacked microelectronic systems [7-8], and the accompanying
challenge of thermal management of multiple, parallel heat
generating planes [2, 9]. In order to fully utilize the electrical
benefit for vertical integration, it is essential that any thermal
penalty associated with 3D ICs be kept to a minimum, and
novel means of cooling of multi-stack systems be investigated.
Several applications of thermal modeling of 3D ICs to
improve their electrical design have also been reported [10].
Each of these applications relies on an accurate method for
temperature estimation in a 3D IC. While the temperature field
in a 3D IC can in principle be determined from a finite-element
simulation, an analytical-based temperature computation
approach is desirable since it provides a better physical
understanding of the thermal problem, and is also easier to
integrate with electrical design tools. Several recent papers have
discussed the thermal modeling and analysis of 3D ICs. A
thermal resistance model of a general, N-layer 3D IC has been
proposed [2]. Analytical models for predicting the temperature
profile on a 3D IC have been developed [4, 11-12]. Compact-

modeling based tools have also been extended to account for
vertically-stacked die [13]. Regardless of the approach used for
temperature computation, the accuracy of the predicted
temperature field depends on accurately knowing the values of
several physical parameters. The inter-die thermal contact
resistance is one of the least well-known among these
parameters, primarily because of difficulties in either
determining it analytically or measuring it experimentally. Some
work on analytical estimation based on a simple thermal
resistance combination has been reported [2], but this does not
account for thermal contact resistance. Very limited work on
experimental thermal measurements on 3D ICs has been
reported. Recently, some work on experimental measurement of
the thermal contact resistance has been reported [5-6].
However, in general, there is a lack of experimental data, which
inhibits the accuracy of computational models since
experimental data often serves to validate computational models
and determine key fitting parameters.
This paper presents experimental results on thermal
performance of a two-die 3D IC. Heaters and temperature
sensor circuits embedded in each layer are utilized to heat and
measure temperature rise in each layer. Both steady-state and
transient data are reported. Results indicate a unique asymmetry
in the thermal performance of the two-die stack.
Section 2 describes the experimental procedure
including the set up for performing the thermal calibration and
measurements. Section 3 presents and discusses results, and
Section 4 provides possible future directions.
2. Experimental Setup
The 3D IC used in this work is a two-die stack comprising a
large die and a smaller die. The smaller die is bonded to the
large die in an asymmetric position. Each die contains an
7 mm
3.5 mm
mm
7 mm
7 mm
3.5
Bottom Die Top Die
Fig.1. Schematic of the two die in the 3D IC. Blue and Red
lines show the heater and sensor respectively. Green circle on
the bottom die shows the location of the center of the top die in
the 3D IC.
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embedded heater and a resistance thermometry based
temperature sensor. Each heater and sensor is accessible via I/O
pads located on the periphery of the bottom die. Heaters are
serpentine structures that cover the entire die in a nearly
uniform fashion in order to simulate uniform die heating. Due to
space constraints on the test vehicle, only one temperature
sensor is provided on each die, and is located at the center of
each die. Specific geometry of the heater and sensor structures,
such as width, thickness, etc. are governed by specific design
rules. Figure 1 shows a schematic of the two-die stack. The 3D
IC is first glued on a leadless chip carrier (LCC) substrate using
a thermally conductive epoxy. In order to access the I/O pads
located on the bottom die, wirebond connections are made
between the die I/O pads and LCC contact pads. Wire bond
integrity is verified by visual inspection under a microscope.
After wire bonding, the LCC substrate is mounted on a
compatible pin socket. Finally, fine electrical wires are soldered
on the socket leads. In this manner, heater and sensor elements
on each die are accessed through I/O pads, wire bonds, LCC
contact pads, socket pins and finally soldered wires. Figure 2
shows the 3D IC in the LCC substrate. Since the die stack
packaging was not carried out in a standard packaging process
flow, the package characteristics here may not be fully
representative of end product packaging of 3D ICs. It is also to
be noted that thermal characteristics of semiconductor systems
are strongly package dependent.
Figures 3(a) and 3(b) show an image of the final,
soldered socket and the experimental setup for thermal
calibration of temperature sensors on each die. Calibration is
carried out by measuring the resistance of each sensor and
heater at several temperatures between 20 °C to 90 °C. A
Boeckel Scientific CCC 0.5d incubator is used for varying the
temperature, and Keithley 2400 and Keithley 2601 instruments
are used for supplying a test current and measuring voltage
respectively. A waiting period of 30 minutes is implemented at
each temperature to eliminate thermal transients. A test current
of only 10 µA is used to minimize self-heating effects.
Fig. 2. An image of the two-die 3D IC on a LCC substrate.
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(a) (b)

Fig. 3. (a) Soldered socket used for accessing thermal features on the 3D IC, (b) Experimental setup for thermal calibration of
temperature sensors on each die.

3. Results and Discussion

Figure 4 shows the electrical resistance of top and bottom die
sensors respectively as functions of temperature. Experimental
data, shown in circles is modeled accurately by a linear fit. The
linear behavior is to be expected, since the electrical resistance
of metals increases linearly around room temperature. The
temperature coefficient of resistivity determined from these
measurements is 0.00374 °C-1 and 0.00369 °C-1 for the top and
bottom sensors respectively. Temperature coefficient of
resistivity for the top and bottom heaters is also measured to be
in the same range, within experimental error bounds. This is in
good agreement with the standard value of thermal coefficient
of resistivity of Aluminum, which is 0.0043 °C-1. Note that
some deviation is to be expected since thermophysical
properties of materials are known to deviate from standard bulk
values.
Calibration curves similar to Figure 4 are generated for
each unit being tested. Once the devices are calibrated, the
measured electrical resistance of each sensor is utilized to
determine its temperature based on its calibration curve.

Fig. 4. Thermal calibration curves for the top and bottom die Fig. 5. Measured temperature rise in each sensor as a function
sensors. of heating in bottom die.

3 Copyright © 2013 by ASME


Fig. 6. Measured temperature rise in each sensor as a function
of heating in top die.
The heating current in either top or bottom heater is then
increased and the effect of sensor temperature is determined.
Figure 5 shows sensor temperature rise as a function of bottom
die heating. Experimental data is modeled well with a linear fit,
as expected from the linearity of the underlying governing
energy equations. Cartoon in Figure 5 shows the ON/OFF state
of each die heater, and the location of the temperature sensors.
The ON heater is represented by a red line. Figure 6 shows
similar data when the top die is heated. In both cases, the
temperature sensor of the layer being heated registers greater
temperature rise. This is expected due to closer proximity of the
top and bottom sensors to the respective heaters.
Fig. 7. Measured temperature rise in top and bottom sensors as
a function of heating in the respective die.
4 Copyright © 2013 by ASME
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Figure.7 plots the temperature rise in the bottom and top
sensors as a result of heating up the respective heater. This data
shows the effect of allocating a given power to either the top or
bottom die. Results indicate that for the same amount of power
dissipated, the top die gets significantly hotter than the bottom
die. The primary reason behind this is that the heat dissipated in
the top die must conduct through the bottom die into the LCC
substrate. Measurements on a packaged two-die stack are
expected to further elucidate the top-bottom asymmetry in a
two-die stack.
4. Conclusions and Future Work
This paper discusses experimental thermal characterization
of a two-die 3D IC using heater and temperature sensor circuits
embedded in each die. The effect of heating one die on itself
and on the other die is explored. Measurements indicate that the
top die heats up more and faster than the bottom die. This is
believed to be related to the packaging of the die.
Measurements presented in this work are expected to enhance
the understanding of heat transport in 3D ICs. Experimental
data is expected to help validate analytical and simulation
models that have been proposed for 3D ICs. This will facilitate
the development and implementation of robust, thermal-aware
design and optimization tools for 3D ICs. While this work is
limited to a two-die stack, similar measurements in the future
may help characterize heat transfer in a multi-die stack with
greater than two die.
ACKNOWLEDGMENT
This material is based upon work supported by the National
Science Foundation under Grant No. CBET-1236370.
REFERENCES
[1] Venkatadri, V., Sammakia, B., Srihari, K., and Santos, D.,
2011, “A review of recent advances in thermal management in
three dimensional chip stacks in electronic systems,” ASME J.
Electronic Packaging, 133, pp. 041011-1.
[2] Jain, A., Jones, R.E., Chatterjee, R., and Pozder, S., 2010,
“Analytical and numerical modeling of the thermal performance
of three-dimensional integrated circuits,” IEEE Trans.
Components Packaging Technol., 33, pp. 56-63.
[3] Jain, A., Alam, S.M., Pozder, S., and Jones, R.E., 2011,
“Thermal–electrical co-optimisation of floorplanning of three-
dimensional integrated circuits under manufacturing and
physical design constraints,” IET Computers & Digital Tech., 5,
pp. 169-178.
[4] Choobineh, L., and Jain, A., 2012, “Analytical solution for
steady-state and transient temperature field in vertically
integrated three-dimensional integrated circuits (3D ICs),”
 Downloaded from http://asmedigitalcollection.asme.org/InterPACK/proceedings-pdf/InterPACK2013/55768/V002T08A034/4463258/v002t08a034-ipack2013-73167.pdf by King Abdullah University For Science and Technology (KAUST) user on 06 April 2022
IEEE Trans. Components Packaging Manufacturing Technol.,
2(12), pp. 2031-2039.

[5] Oprins, H., Cherman, V.O., Vandevelde, B., Van der Plas,
G., Marchal, P., and Beyne, E., 2012, “Numerical and
experimental characterization of the thermal behavior of a
packaged DRAM-on-logic stack,” Proc. IEEE Electron.
Components Technol. Conf., pp. 1081-1088.

[6] Colgan, E.G., Andry, P., Dang, B., Magerlein, J.H., Maria,
J., Polastre, R.J., and Wakil, J., 2012, “Measurement of
microbump thermal resistance in 3D chip stacks”, Proc. IEEE
SEMI-Therm Symp., pp. 1-7.

[7] Black, B., Annavaram, M., Brekelbaum, N, et al., 2006,

“Die stacking (3D) microarchitecture,” Proc. 39th IEEE/ACM
Int. Symp. Microarchitecture, pp. 469-479.

[8] Alam, S.M., Jones, R.E., Pozder, S., and Jain, A., 2009,
“Die/wafer stacking with reciprocal design symmetry (RDS) for
mask reuse in three-dimensional (3D) integration technology,”
Proc. IEEE Intern. Symp. Quality Electron. Design, pp. 569-
575.

[9] Jones, R., 2007, “Technology, design and applications of

3D integration,” Proc. SEMATECH Conf. on Thermal and
Design Issues in 3D ICs.

[10] Alam, S.M., Jones, R.E., Pozder, S., Chatterjee, R., and
Jain, A., 2010, “New design considerations for cost effective
three-dimensional (3D) system integration,” IEEE Trans VLSI
Syst., 18, pp. 450-460.

[11] Haji-Sheikh, A., Beck, J.V., and Agonafer, D., 2003,

“Steady-state heat conduction in multi-layer bodies,” Inter. J.
Heat Mass Transfer, 46, pp. 2363-2379, 2003.

[12] Geer, J., Desai, J., and Sammakia, B., 2007, “Heat
conduction in multilayered rectangular domains,” ASME J.
Electronic Packaging, 129, pp. 440-451.

[13] Skadron, K. Sankaranarayanan, K., Velusamy, S. Tarjan,

D., Stan, M.R., and Huang, W., 2004, “Temperature-Aware
Microarchitecture: Modeling and Implementation,” ACM Trans.
Architecture & Code Optimization, 1(1), pp. 94-125.

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