To accomplish these tasks, you can follow the following steps:

1. Reading the data:

 Configure the FPGA board to read the digital data coming from the ADC.
 Use the appropriate interface (e.g., SPI, I2C, etc.) to communicate with the
ADC and read the analog waveforms.
 Store the values in a buffer in the FPGA board's memory.
2. Finding the peaks:
 Process the data buffer to detect the peaks of the waveform. You can use
various peak detection algorithms, such as the threshold-based,
derivative-based, or wavelet-based methods.
 Once you have detected the peaks, calculate the summation and
difference of the peak values.
3. Computing the ratio:
 Divide the difference of the peak values by the summation of the peak
values to obtain the ratio.
 Store the ratio in a register.
4. Comparing with the look-up table:
 Read the look-up table from a text file and store it in the FPGA board's
memory.
 Search the table for the value that matches the ratio obtained in step 3.
 Store the corresponding value in a register.
5. Displaying the result:
 Connect a 7-segment display to the FPGA board.
 Write the value stored in the register to the display.

Note that the exact implementation details will depend on the specific FPGA board and
ADC you are using, as well as the programming language and tools you are using to
develop the FPGA design

//sample code is given

“This code assumes that the ADC's serial interface uses SPI mode 0 and that the adc_cs signal is
connected to the chip select pin of the ADC. The code also stores the ADC data in a buffer and
increments an index to cycle through the buffer. You can modify this code to implement your
specific requirements for peak detection and ratio calculation.”
Sample code 1 explanation:

This is a Verilog module for an ADC peak detection system, with a few key
features:

 The module reads data from two ADC channels and stores it in memory
(data_buf_ch1 and data_buf_ch2).
 It uses clock edge detection to advance an index (called "index")
through the memory array, so that each new data point is stored in the
next slot.
 It has logic to control the ADC (using adc_sdi and adc_cs signals) and
read data from it.
 It includes a lookup table (LUT) that maps ratios between peak values to
values to display on a 7-segment display.
 It includes outputs for the 7-segment display segments (seg_a, seg_b,
etc.) and for the ADC channels (adc_ch1 and adc_ch2).

Here's a breakdown of the key parts of the code:

 The module declaration defines the input and output signals for the
module, including the clock (clk), reset (resetn), ADC chip select (adc_cs),
ADC serial data in (adc_sdi), ADC channel outputs (adc_ch1 and
adc_ch2), and 7-segment display segments (seg_a through seg_g).
 The code initializes some key variables at the beginning of execution,
including the memory arrays for storing ADC data (data_buf_ch1 and
data_buf_ch2) and the index variable (which starts at 0).
 The "clock edge detection" block runs on every positive edge of the
clock (and on the negative edge of the reset signal). It reads the data
from the ADC memory arrays at the current index value, and increments
the index (or resets it to 0 if it has reached the end of the memory
array).
 The "ADC read logic" block also runs on every positive edge of the clock
(and on the negative edge of the reset signal). It selects the ADC, waits
for a conversion to complete, reads the conversion result for both
channels, and deselects the ADC.
 The "ADC control logic" block also runs on every positive edge of the
clock (and on the negative edge of the reset signal). It controls the ADC
 using the adc_sdi and adc_cs signals, which are set to 0 and
0b1111_1110 (respectively) when the system is reset.
2. sample code 2
Tb1sample 1:

In this testbench, we first declare the inputs and outputs of the adc_peak_detection module
as reg and wire variables, respectively. We then instantiate the DUT using these variables.

We generate a clock signal using an initial block and reset the DUT using another initial
block. We then write test vectors to the adc_sdi input of the DUT using another initial
block.

Finally, we monitor the outputs of the DUT using an always block that triggers on the
positive edge of the clock signal. Within this block, we can use $display or $monitor
statements to print the output values to the console or write them to a waveform file for
later analysis.

Note that the exact test vectors and output monitoring code will depend on the specific
requirements of the design and the test plan.

Tb2 sample 1

This testbench initializes the module inputs, performs some test read and
write of ADC registers, and tests the ADC conversion and channel selection by
simulating 2048 clock cycles and changing the input adc_sdi accordingly. It also
tests the 7-segment display by iterating over a lookup table LUT of
hexadecimal digits and setting the corresponding segments seg_a to seg_g.
Finally
Re