Proceedings of the Third International Conference on Intelligent Communication Technologies and Virtual Mobile Networks (ICICV 2021).
IEEE Xplore Part Number: CFP21ONG-ART; 978-0-7381-1183-4
Design of Two Stage Operational Amplifier and
2021 Third International Conference on Intelligent Communication Technologies and Virtual Mobile Networks (ICICV) | 978-1-6654-1960-4/20/$31.00 ©2021 IEEE | DOI: 10.1109/ICICV50876.2021.9388589
Implementation of Flash ADC
Pabba Sowmya
M . Tech Scholar
Electronics & Communication
Engg.
GRIET
Hyderabad, India
sowmyagoud217@gmail.com
Abstract—In this paper, Flash Analog to digital converter is
implemented whose resolution is 3-bits. The designed Flash ADC
consists of a resistive ladder network, comparators, the
thermometer to a binary encoder and the entire design is carried
out using LTspice tools employing 180nm technology. The
reference voltage applied to the resistive ladder network is 1.8V.
A two-stage operational amplifier is used as a comparator in the
flash ADC. Binary code is obtained from the thermometer code
by utilizing a priority encoder. The major problem that usually
appears in flash ADC is as the number of resolution bits
increases, the Area, as well as the power consumption of the
circuit, also increases. In this paper, we principally concentrated
to lessen the power consumption of the ADC by optimizing
encoder circuitry. With the purpose of reducing power
consumption, Encoder is implemented using 2:1 mux based on
various logics such as switch logic, pass transistor logic as well as
CMOS logic. In addition to this, the Wallace tree encoder was
also implemented. Performance parameters of Flash ADC such
as conversion time as well as average power are calculated and
compared. It is verified average power obtained using Wallace
tree encoder is 910pW and it is less compared to encoder
implemented with other designs.
Keywords—Average power, Conversion time, Thermometer to
binary encoder, comparator.
I. INT RODUCT ION
Digital signal processing has advanced intensely due to the
rapid expansion of science and technology. In the majority of
the digital domains, signal processing offers several advantages
such as flexibility in design and programmability, reduced
silicon area, high accuracy, as well as a smaller amount of
power consumption. The design process is cost-effective and
faster. Hence it is possible to design a system with a lesser area
along with high speed. It is required to have an analog to digital
converter that offers much higher speed in wireless
communication, image processing, etc[1].
It is preferred to have digital systems that are portable and
have prolonged battery life. This can be only possible by
developing applications that consume less power. Since ADC’s
act as front-end components in the majority of mixed-signal
systems, we focused to design ADC that consumes less power
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Mamatha Samson Mohd Javeed Mehdi
Professor Assistant Professor
Electronics & Communication Electronics & Communication
Engg. Engg.
GRIET GRIET
Hyderabad, India Hyderabad, India
mamata2001@g mail.co m javeed954@grietcollege.com
which in turn offers higher speed. We have various types of
ADC architectures for instance successive approximation type
ADC, Flash type, sigma-delta, etc. Among these Flash ADC is
preferred since it offers high speed because of its parallel
architecture, the conversion time is not limited by resolution
hence these ADC’s are utilized in those systems where
bandwidth with a wide range and high speed is required[2].
Al-Ahsan Talukder and Shamim Sarker have implemented
flash ADC with 3-bit employing threshold inverter
quantization(TIQ). The main feature of this technique is the
absence of separate reference voltage power supplies, unlike
other Flash ADC implementations. It is possible to set the
switching voltage of the inverter by choosing nmos as well as
pmos transistors with suitable width to length ratios. Th is
architecture comprises of TIQ comparator, the thermometer to
the binary encoder in addition to gain booster. Because of the
change in the dimensions of comparator Area changes [3].
Sonu Kumar and Anjali Sharma proposed a strategy
employing CMOS technology that is demonstrated for
implementing opamp. They preferred CMOS technology for
designing an operational amplifier due to the fact that CMOS
devices consume low static power and these devices are highly
withstanding noise. The two-stage operational amplifier
performance parameters are obtained whose gain is 44.98dB,
the phase margin is 63 degrees, the gain-bandwidth product is
33.4MHz, power consumption 276μW[4].
Mirza Nemeth Ali Baig and Rakesh Ranjan have
implemented high-speed flash ADC for wireless LAN
applications. The designed 3-bit flash ADC is implemented
using seven operational transconductance based comparators
with the reference voltage of 250mV and a high-speed encoder
is implemented using full adders. This design is a flash -based
ADC converter with a finite output resolution of three bits and
power consumption of about 223μW and resides in a chip area
of 0.089287 mm2. The high-speed flash ADC is being
designed and verified using the CADENCE Virtuoso tool with
CMOS 180 nm technology. Since ADC is implemented by
utilizing a full adder based encoder, The area is limited by the
resolution[5].
490
 Proceedings of the Third International Conference on Intelligent Communication Technologies and Virtual Mobile Networks (ICICV 2021).
IEEE Xplore Part Number: CFP21ONG-ART; 978-0-7381-1183-4

Sarojini Mandal and J.K.das had implemented a 3-bit flash Resolution of flash ADC does not determine accuracy , it just
ADC using cascading full adder by using pass transistor logic indicates the total bits that are obtained at the output side.
that makes the circuit much faster. They have improved the
efficiency of flash ADC by improving the working of the
comparator by scaling down the length to width ratio of
transistors assuming transistors operating in the saturation
region. The gain of comparator increased by proper sizing o f
transistors. The encoder circuit is designed using a full adder
with 10 transistors. Chip complexity and area are reduced using
pass transistor logic employed in a full adder circuit. As full
adder is designed using pass transistor, logic levels will
deteriorate[6].
Jayesh. J. Vyas implemented flash ADC comprising 3-bit
resolution employing 180-nanometer technology files using
NGspice tool for high-speed applications. The response time of
the ADC and the comparator was calculated as 4.9 ns and
3.7ns. Power consumed by ADC is given as 50μW. Encoder
circuit is implemented using basic gates. The gate delay for the
inverter, two-input, three-input, and four-input NAND gates
are given as 0.29ns, 0.51ns, 0.37ns, 1.06ns respectively with Fig 1: 3-bit Flash ADC block diagram
2ns rise time and fall time for inputs. Comparator sensitivity
and comparator gain are calculated as 11mV and 29dB A. Resistive Ladder Network
respectively. the main drawback is delay increases linearly with
resolution since NAND gates were used[7].
Piyush V. konodiya had implemented flash ADC for high -
speed ultra wideband communications(it’s a form of
technology whose signal bandwidth is greater than 500MHz). .
Flash ADC employing ROM based encoder is designed and
reported Conversion time, as well as the power consumption of
the circuits, are given as 13.64mW and 1.135ns respectively. It
is not possible to suppress bubble errors utilizing a ROM
encoder because it is slow[8].
II. FLASH ADC ARCHITECTURE
Fig 2: Resistive Ladder Network
To implement N bit flash ADC, we require 2N -1 Figure 2 shows resistive ladder network. In this
comparators are needed. Similar to opamp, the comparator paper, we have implemented 3-bit flash ADC comprises of
comprises of two inputs where analog input is given to the resistive ladder network. It is possible to provide a steady
inverting terminal and reference voltage is applied to non- reference voltage to the comparators utilizing the resistive
inverting terminal. Comparators are divided with the help of ladder network. 2N resistors are required to design N-bit Flash
the resistive ladder network. 2N resistors are utilized to form a ADC. The main function of this ladder network is that it
resistive ladder network of N bit. Since we have implemented divides reference voltage across all resistors such that the
3-bit, the number of res istors required will be eight. The difference between the reference voltage of the corresponding
reference voltage is generated across the resistive ladder
two comparators will be the least significant bit value. Since
network between reference voltage and ground is equally
we have given reference voltage of 1.8 volts, each comparator
distributed and is differed by the least significant bit. the
comparator compares the reference voltage signal with the reference voltage will be differed by 255mV.
input analog signal and indicates output as logic high whenever B. Operational amplifier as comparator
analog input exceeds reference voltage and indicates logic low
output when analog input is smaller than reference voltage. The
output of comparators forms a thermometer code. Further, we
need to translate thermometer code into binary code[9].
The output generated mainly depends on the resolution. But
the major disadvantage is as the resolution increases, th e
number of comparators required will get increases . For
example if we need to implement flash ADC of 9 bit, we need Fig 3: Comparator block diagram
511 comparators which occupy a huge die area and dis sipates a Figure 3 shows comparator block diagram. The
large amount of power. Hence we need to reduce the power applied input signal is compared with the reference signal and
and area of flash ADC as they are major constraints. will provide output as shown below[11].

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 Proceedings of the Third International Conference on Intelligent Communication Technologies and Virtual Mobile Networks (ICICV 2021).
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Whenever, III. THERMOMETER TO BINARY ENCODER DESIGN

Vinput>Vref ; Voutput =Logic High (1)
Vinput<Vref; Voutput=Logic Low (2)
Figure 2 shows a block diagram of the two-stage opamp. It
consists of a differential voltage gain stage followed by a
common source gain stage. Differential inputs are applied
through the M1 transistor along with the M2 transistor. Opamp
Biasing is furnished with the transistors M5 and M8 to ensure
all transistors in saturation. the current mirror formed by the
transistor M3 and M4 mirrors current from transistor M1 and is
subtracted from the transistor M2. If sufficient gain is not
obtained during the differential stage then we use a common
source amplifier as the gain stage which is formed by
transistors M6 and M7.
Fig 4: Block diagram of two stage opamp .
AND SIMULATION
Thermometer code can be translated to binary code in
different ways. The name thermometer code is given because
the output of the comparators looks like thermometer reading
that is as the value increases the number of ones goes on
increasing same like the mercury level which increases as
temperature increases. There are different types of encoders to
convert thermometer code into binary code for instance
Wallace tree encoder, encoder design utilizing mux, and
encoder using xor as well as ROM encoder. Each of these
encoders has its own advantages and disadvantages[11].
The structural design of mux based encoder is simple.
The circuit is implemented using 2:1 mux and hence It has a
small critical path in comparison to the Wallace tree encoder.
Encoder designed using Mux operates on the simple logic that
is if half of the thermometer code represents logic high the
most significant bit in binary code is also high. The value
corresponding to 2n-1 represents MSB in the binary output.
Again this thermometer code is classified into two codes to
find next binary output. A select line of the second stage Mux
is obtained from the preceding stage mux output. The
procedure is continued till the end of the last 2:1 mux and the
least significant bit of binary output is obtained. Even if
resolution increases we can implement an encoder using this
2:1 mux easily with less area and less power consumption[11].
T ABLE 1: T HERMOMET ER T O BINARY CODE CONVERSION

In this paper, the comparator is operated with sinusoidal T0 T1 T2 T3 T4 T5 T6 B0 B1 B2

input of 1.8 volts. It compares with the reference voltage
which is obtained from the resistive ladder network and 0 0 0 0 0 0 0 0 0 0
provides logic high or logic low. Ultimately square waveform 0 0 0 0 0 0 1 0 0 1
will be generated which is shown in figure 6.
0 0 0 0 0 1 1 0 1 0
0 0 0 0 1 1 1 0 1 1
0 0 0 1 1 1 1 1 0 0
0 0 1 1 1 1 1 1 0 1
0 1 1 1 1 1 1 1 1 0
1 1 1 1 1 1 1 1 1 1

We have implemented the Wallace tree encoder in this

Fig 5: T wo stage opamp as comparator paper. The critical function of this encoder is that the number
of ones attained at the comparator output is counted. Full adder
is the most fundamental building block to form the Wallace
tree encoder. The number of full adders required to form the
Wallace tree encoder is calculated by using the formula 2n -n-1.
Where n signifies the number of bits of ADC.
Initially, all the comparator outputs are given as inputs to
the full adder cells. Each full adder cell adds three bits and
gives sum and carry during the first stage. Again all the sums
are forwarded to the next full adder cell and carry to another
adder cell. Using this type of encoder we can achieve bubble
error suppression/compression. It is unlike to fat tree encoder
Fig 6: Comparator results

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where bubble error suppression takes place using NAND gates Figure 9 shows the implementation of a full adder employing CMOS
technology. we can obtain sum and carry by adding input bits say for instance
with two or more inputs. if we apply input ABC as 111 the corresponding sum, as well as carry, will be 1
It is the simplest possible method to convert a thermometer and so on.
to binary code. All available inputs get passed across an equal
number of full adders hence propagation delay of all applied
inputs are the same which is the main benefit of this encoder
type. The speed of the encoder is high since it exhibits
pipelining.
As resolution increases the number of full adders to convert
thermometer code to binary code also increases. Hence area
occupied by the encoder will be increased that leads to large
power dissipation and chip cost.
A. Full adder implementation
Here we have implemented a simple one-bit conventional Fig 10: Full adder output
full adder with 14 PMOS and 14 NMOS transistors. Two
inverters are used to convert inverted sum and carry. Using the B. Wallace Tree Encoder
boolean function we can realize gate-level implementation and By utilizing adder, the Wallace tree encoder is built as it is
also we can design a transistor-level schematic for both sum the most elementary building block. As we are trying t o
and carry. The carry out internal node is forwarded to obtain implement a 3-bit flash ADC, the number of full adders needed
sum[16]. is four. The obtained number of ones on the comparator output
A schematic of the full adder is shown below is counted by the Wallace tree. The dominant problem is as
resolution increases, the number of full adders will be
Here, Sum =(A ْ B) ْ Cin) (3) increased. As full adder consumes more area, power
=A(B)’Cin+(A)’Bcin+AB(Cin)’+ABCin (4) consumption will be high. So here we are replacing full adders
with 2 to 1 multiplexer[12].
=[CO’*(ABCin)+(A+B+Cin)]’ (5)
Carry output=(A*B)+(B*C)+(A*C)
=A*B+Cin*(A+B) (6)

Fig 11: Wallace tree encoder block diagram

Fig 7: Full adder Schematic

Fig 12: Wallace tree encoder output

C. 2:1 Multiplexer(Mux) Based Encoder

Fig 8: T he implementation of full adder in LT spice

Fig 13: Encoder implementation using 2:1 Multiplexer

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D. 2:1 Multiplexer Using Various Logic Styles that leads to the increase of parameters like area, power as well
as delay[15].
i) 2:1 Mux Using Switch Logic(Transmission Gate)

IV RESULTS

Transient Analysis
Transient analysis: Transient analys is is performed by
applying a sinusoidal waveform with a voltage of 1.8 volts by
applying a frequency of 1KHz and average power is
calculated.

Fig 14: 2:1 mux using switch logic

The figure 14 shows the implementation of the encoder
using a 2:1 multiplexer. Due to the implementation of mux
using CMOS transmission gate, the number of transistors got
reduced which reduced the power consumption, area and
increases speed. The power consumed by the flash ADC is Fig 17: 3- bit Flash ADC using Wallace tree encoder
calculated as 345 μW.
ii) 2:1 Mux Using pass transistor logic

Fig 18: 3-bit Flash transient analysis

Fig 15: 2:1 mux using pass transistor logic
Figure 15 shows 2:1 mux using pass transistor logic.
Here we have utilized only two transistors to implement mux.
logic levels getting deteriorate using pass transistors. so to
overcome that buffer is inserted to obtain a strong one and
strong zero[13].
ii) 2:1 Mux Using Complementary metal-oxide-semiconductor
(CMOS) logic
A. Average Power
Designing low power portable design systems is the main
challenge. power consumption of the circuit is reduced by
introducing various logic design styles in CMOS technology.
in CMOS circuits, the average power is estimated as the sum of
static power, dynamic power as well as switching power. the
average power calculation is shown in the equation below.
Average power of the 3-bit Flash ADC using Wallace tree
encoder is 910pW[14].
Paverage=Pstatic+Pdynamic+Pswitching (7)

Fig 19: Average power calculation of 3-bit Flash ADC

Fig 16: 2:1 mux using CMOS logic

Figure 9 shows the implementation of a 2:1 multiplexer
using Complementary metal-oxide-semiconductor
technology(CMOS). The main advantage of this technology is
that any boolean function can be implemented by utilizing
PMOS transistors in a pull-up network whereas a pull-down
network is designed utilizing NMOS transistors and output is
obtained between power and ground terminals. The major Fig 20: Average power calculation of 3-bit Flash ADC
drawback of this topology is as the number of transistors rises

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B. Conversion time D. 3-bit Flash ADC using pass transistor results

conversion time is one of the main parameters in flash ADC.

Flash ADC is faster because to convert analog to digital signal
requires only one clock cycle. The amount of time that is
required to make analog signal to digital signal. the maximum
frequency of operation is obtained using conversion time.

Fig 25: 3-bit Flash ADC using pass transistor logic 2:1 multiplexer

Fig 21: Conversion time calculation

Figure 21 shows conversion time calculation. T he time taken by Fig 26: Average power calculation for 3-bit Flash ADC using pass transistor
the 3-bit Flash ADC to convert analog signal to digital signal is 76ns. logic
C. 3-bit Flash ADC using switch logic results

Fig 27: Conversion time calculation

E. 3-bit Flash ADC using CMOS logic Results

Fig 22: 3-bit Flash ADC using switch logic 2:1 multiplexer

Fig 28: Implementation of 3-bit Flash ADC using CMOS logic

Fig 23: Average power calculation for 3-bit Flash ADC using switch logic
encoder

Fig 29: Average Power Calculation

Fig 24: Conversion time calculation Fig 30:Conversion time calculation

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V. COMPARISON [5] Mirza Nemath Ali Baig, Rakesh Ranjan, “ Design and
T ABLE II: 3-BIT FLASH ADC PARAMET ER COMPARISON implementation of 3-bit High-speed flash ADC for wireless
LAN Applications”, IJARCCE, Vol 6, 2017.
Using Using Using Using CMO S [6] Sarojini Mandal, Dr. J.K Das, “ Design of 3-bit low power
Wallace Pass switch 2:1 mux flash ADC”, IJARCET, Volume 3 issue 4, April 2014.
tre e transistor logic 2:1 [7] Jayesh J. Vyas ,” Simulation of 3 bit Flash ADC in 0.18um
e ncoder logic 2:1 mux technology using Ngspice Tool for High-speed applications”,
IJSRD, volume 1, Issue 2, 2013.
mux
[8] Piyush. V. Kanodiya, Amisha. P. Naik, “Analysis and
Average 910pW 371μW 345μW 1.372nW design of flash Analog to digital converter for ultra-wideband
power applications”, IEEE 2011.
Resolution 3 bits 3 bits 3 bits 3 bits [9] Pradeep Kumar, AmitKolhe, "Design & Implementation of
Low Power 3-bit Flash ADC in 0.18μm CMOS", International
Journal of Soft Computing and Engineering (IJSCE), ISSN:
Conversion 74.2ns 124.7ns 189 ns 55 ns
2231-2307, Volume-1, Issue-5, November 2015.
speed
[10] Ashima Gupta, anil Singh, “Highly digital voltage
scalable 4-bit flash ADC”, IET circuits, devices &systems,
VI. CONCLUSION 2019.
[11] M.P. Ajanya, George Tom, “ Thermometer code to binary
In this paper, we have implemented flash ADC with a code converter for flash ADC –A Review”, ICCPCCT, 2018.
3-bit resolution. Design and simulation of 3-bit flash ADC are [12] M.P. Ajanya, George Tom, “Low power Wallace tree
carried out using the LTspice tool employing 180nm encoder for flash ADC”, IOP conference series: Material
technology model files. Parameters such as conversion time, science and engineering 2018.
the average power of 3-bit flash ADC are calculated and [13] Anjum Aara, “Design and implementation of CMOS and
compared. Mainly we focused to reduce the power CNT based 2:1 multiplexer at 32nm technology”, IJRET,
consumption of 3-bit flash Adc by optimizing the encoder Volume 6, August 2019.
circuitry. The encoder is implemented using different design [14] Neil H.E. Weste, David Harris “CMOS VLSI Design”.
styles such as Wallace tree encoder, 2:1 mux based encoder. It [15] G. Tretter, M. Khafaji, D. Fritsche, C. Carta And F.
is verified that 3 bit Flash ADC designed utilizing a Wallace Ellinger, "A 24 Gs/S Single-Core Flash Adc With 3 Bit
tree encoder offers less power compared to a 2:1 mux based Resolution In 28 Nm Low-Power Digital Cmos," 2015 Ieee
encoder. Also, we have implemented a 2:1 mux based Radio Frequency Integrated Circuits Symposium (Rfic),
encoder employing different design logics such as switch Phoenix, Az, 2015,
logic, pass transistor logic, and complementary metal-oxide-
semiconductor logic. out of these logics, 3-bit Flash ADC
implemented utilizing encoder with CMOS 2:1 mux consumes
less power and offers less delay. Further, it is intended to
increase the resolution of flash ADC and also to reduce the
average power consumed by the circuit by optimizing the flash
ADC circuitry.

VII. REFERENCES

[1] Glyny George, A. V. Jos Prakash, “Design of ultra-low-

voltage high speed flash ADC in 45nm CMOS Technology”,
IEEE Conference on recent trends in electronics, Information
&communication technology, 2018.
[2] S. Veeramachanen, A. M. Kumar, V. Tummala and M. B.
Srinivas, "Design of a Low Power, Variable-Resolution Flash
ADC," 2009 22nd International Conference on VLSI Design,
New Delhi, 2009
[3] Al-Ahsan Talukder, Md. Shamim Sarker, “A three-bit
threshold inverter quantization based CMOS flash ADC”,
2017 4th International Conference on Advances in Electrical
Engineering, 2017.
[4] Sonu Kumar, Anjali Sharma, “Design of CMOS
operational amplifier in 180nm technology", International
journal of innovative research in computer and communication
engineering Vol.5, issue 4, April 2017.

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