Memory Management

Introduction to Memory Management

Main memory and the registers built into the processor itself are
the only general-purpose storage that the CPU can access
directly.
Data not in memory, must be moved there before the CPU can
operate on it.
Registers that are built into the CPU are quickly accessible.
Transaction on the memory bus is more time consuming.
➢ CPU needs to stall, since doesn’t have data.
➢ Remedy: add fast memory between the CPU and main
memory
We must also protect the operating system from access by user
processes.
On multiuser systems, we must additionally protect user
processes from one another.
➢ Protection is provided at the hardware level.

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 Introduction to Memory Management

Concerns that need to be addressed:

Each process has a separate memory space.
Separate per-process memory space protects the processes
from each other and
Facilitates concurrency i.e., having multiple processes
loaded in memory
To separate memory spaces, we need the ability to
determine the range of legal addresses
We can provide this protection by using two registers,
usually a base and a limit,

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 Base and Limit Registers
A pair of base and limit registers define the logical address space
The base register holds the smallest legal physical memory
address; the limit register specifies the size of the range.
CPU must check every memory access generated in user mode to
be sure it is between base and limit for that user

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 Hardware Address Protection

▪ Any attempt by a program executing in user mode to access

operating-system memory or other users’ memory results in a trap
to the OS, which treats the attempt as a fatal error.
▪ The base and limit registers can be loaded only by the
operating system, which uses a special privileged instruction.
▪ Privileged instructions → kernel mode… hence only OS can load
both base and limit registers.

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Memory Allocation Methods

CONTIGUOUS VS. NON-CONTIGUOUS

MEMORY ALLOCATION

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Memory allocation: Fixed Partitioning
Simplest method for allocating memory is to divide
memory into several fixed-sized partitions.
Each partition may contain exactly one process.
Degree of multiprogramming is bound by the number
of partitions!!!
Equal-size partitions
Any process whose size is less than or equal to
the partition size can be loaded into an available
partition
The operating system can swap a process out of a
partition
If none are in a ready or running state

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 Fixed Partitioning Problems

A program may not fit in a partition.

The programmer must design the program with overlays
Main memory use is inefficient.
Any program, no matter how small, occupies an entire partition.
This results in internal fragmentation.

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 Solution – Unequal Size Partitions

In the variable-partition scheme, the operating system keeps

a table indicating which parts of memory are available and which
are occupied.
At any given time, then, we have a list of available block sizes
and an input queue.
The operating system can order the input queue according to a
scheduling algorithm.
Lessens both problems
but doesn’t solve completely
Programs up to 16M can be accommodated without overlay
Smaller programs can be placed in smaller partitions,
reducing internal fragmentation

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Multiple-partition allocation – Variable size
Multiple-partition allocation - MVT
Variable-partition sizes for efficiency (sized to a given process’ needs)
Hole – Initially, all memory is available for user processes and is considered
one large block of available memory, a hole.
When a process arrives and needs memory, the system searches the set
for a hole that is large enough for this process. If the hole is too large, it is
split into two parts.
One part is allocated to the arriving process; the other is returned to the set
of holes.

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 Multiple-partition allocation
Multiple-partition allocation - MVT
When a process terminates, it releases its block of memory, which is then
placed back in the set of holes.
If the new hole is adjacent to others, these adjacent holes are merged to
form one larger hole.
Operating system maintains information about:
a) allocated partitions b) free partitions (hole)

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 Dynamic Storage-Allocation Problem
How to satisfy a request of size n from a list of free holes?

First-fit: Allocate the first hole that is big enough

Best-fit: Allocate the smallest hole that is big enough; must

search entire list, unless ordered by size
Produces the smallest leftover hole

Worst-fit: Allocate the largest hole; must also search entire list
Produces the largest leftover hole

First-fit and best-fit better than worst-fit in terms of speed and storage
utilization

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 Fragmentation
Both the first-fit and best-fit strategies for memory allocation
suffer from external fragmentation.
External Fragmentation – total memory space exists to
satisfy a request, but it is not contiguous
In the worst case, we could have a block of free (or wasted)
memory between every two processes.
Internal Fragmentation – allocated memory may be slightly
larger than requested memory; this size difference is memory
internal to a partition, but not being used
Depending on the total amount of memory storage and the
average process size, external fragmentation may be a minor
or a major problem.

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 Fragmentation
Statistical analysis of first fit, for instance, reveals that, even
with some optimization, given N allocated blocks, another 0.5
N blocks will be lost to fragmentation.
That is, one-third of memory may be unusable!
* 1/3 may be unusable -> 50-percent rule
This property is known as the 50-percent rule.

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 Fragmentation Removal

Reduce external fragmentation by compaction

Shuffle memory contents to place all free memory together
in one large block
Compaction is possible only if relocation is dynamic, and is
done at execution time
If addresses are relocated dynamically, relocation requires
only moving the program and data and then changing the
base register to reflect the new base address.

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 Swapping
A process can be swapped temporarily out of memory to a
backing store, and then brought back into memory for continued
execution
Total physical memory space of processes can exceed
physical memory
Backing store – fast disk large enough to accommodate copies
of all memory images for all users; must provide direct access to
these memory images
Roll out, roll in – swapping variant used for priority-based
scheduling algorithms; lower-priority process is swapped out so
higher-priority process can be loaded and executed
Major part of swap time is transfer time; total transfer time is
directly proportional to the amount of memory swapped
System maintains a ready queue of ready-to-run processes
which have memory images on disk

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Schematic View of Swapping

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 Context Switch Time including Swapping

If next processes to be put on CPU is not in memory, need to

swap out a process and swap in target process
Context switch time can then be very high
100MB process swapping to hard disk with transfer rate of
50MB/sec
Swap out time of 2000 ms
Plus swap in of same sized process
Total context switch swapping component time of 4000ms
(4 seconds)
Can reduce if reduce size of memory swapped – by knowing
how much memory really being used

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 Context Switch Time and Swapping (Cont.)

Other constraints as well on swapping

Pending I/O – can’t swap out as I/O would occur to wrong
process
Or always transfer I/O to kernel space, then to I/O device
 Known as double buffering, adds overhead
Standard swapping not used in modern operating systems
But modified version common
 Swap only when free memory extremely low

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 Address Binding
mapping the program's logical or virtual addresses to corresponding physical
or main memory addresses
Programs on disk, ready to be brought into memory to execute from an
input queue
Without support, must be loaded into address 0000
Further, addresses represented in different ways at different stages of a
program’s life
Source code addresses usually symbolic i.e. in variable names e.g.
count, i etc
Compiled code addresses bind to relocatable addresses
 i.e. “14 bytes from beginning of this module”
Linker or loader will bind relocatable addresses to absolute addresses
 i.e. 74014
Each binding maps one address space to another

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 Binding of Instructions and Data to Memory

Address binding of instructions

and data to memory addresses
can happen at three different
stages
Compile time: If you know
at compile time where the
process will reside in
memory, then absolute code
can be generated. (e.g, a
user process will reside
starting at location R, then
the generated compiler code
will start at that location and
extend up from there).

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Binding of Instructions and Data to Memory

Load time: If it is not known at

compile time where the process
will reside in memory, then the
compiler must generate
relocatable code. In this case,
final binding is delayed until
load time.
Execution time: If the process
can be moved during its
execution from one memory
segment to another, then
binding must be delayed until
run time.
 Need hardware support for
address maps (e.g., base
and limit registers)

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 Dynamic Linking
So far… it has been necessary for the entire program and all
data of a process to be in physical memory for the process to
execute.
The size of a process has thus been limited to the size of
physical memory.
To obtain better memory-space utilization, we can use dynamic
loading:
1. A routine is not loaded until it is called.
2. All routines are kept on disk in a relocatable load format.
3. Main program is loaded into memory
4. When a routine needs to call another routine, relocatable linking loader is
called to load the desired routine into memory.
5. Control is transferred to new routine.

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 Dynamic Linking
Static linking – system libraries and program code
combined by the loader into the binary program image
Dynamic linking –linking postponed until execution time
Small piece of code, stub, used to locate the appropriate
memory-resident library routine
Stub replaces itself with the address of the routine, and
executes the routine
Operating system checks if routine is in processes’
memory address
If not in address space, add to address space
Dynamic linking is particularly useful for libraries
System also known as shared libraries

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 Logical vs. Physical Address Space

The concept of a logical address space that is bound to a

separate physical address space is central to proper memory
management
Logical address – generated by the CPU; also referred to
as virtual address
Physical address – address seen by the memory unit
Logical address space is the set of all logical addresses
generated by a program
Physical address space is the set of all physical addresses
generated by a program

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 Memory-Management Unit (MMU)
Hardware device that at run time maps virtual to physical address
To start, consider simple scheme where the value in the relocation
register is added to every address generated by a user process at the
time it is sent to memory
Base register now called relocation register
MS-DOS on Intel 80x86 used 4 relocation registers
The user program deals with logical addresses; it never sees the real
physical addresses
Execution-time binding occurs when reference is made to location
in memory
Logical address bound to physical addresses

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 Dynamic relocation using a relocation register

Routine is not loaded until it is called

Better memory-space utilization;
unused routine is never loaded
All routines kept on disk in relocatable
load format
Useful when large amounts of code
are needed to handle infrequently
occurring cases
No special support from the operating
system is required
Implemented through program
design
OS can help by providing libraries to
implement dynamic loading

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Hardware Support for Relocation and Limit Registers

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Paging
 Paging
Physical address space of a process can be noncontiguous; process
is allocated physical memory whenever the latter is available
Avoids external fragmentation
Avoids problem of varying sized memory chunks
Divide physical memory into fixed-sized blocks called frames
Size is power of 2, between 512 bytes and 16 Mbytes
Divide logical memory into blocks of same size called pages
Keep track of all free frames
To run a program of size N pages, need to find N free frames and
load program
Set up a page table to translate logical to physical addresses
Every process has its own page table
Backing store likewise split into pages
Still have Internal fragmentation

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 Address Translation Scheme
Address generated by CPU is divided into:
Page number (p) – used as an index into a page table which
contains base address of each page in physical memory
Page offset (d) – combined with base address to define the
physical memory address that is sent to the memory unit

m = logical address

Size of logical address space = 2m

page size = 2n
# of pages = 2m-n

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Paging Hardware

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Paging Model of Logical and Physical Memory

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 Paging Example

n=2 and m=4 32-byte memory and 4-byte pages

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 Paging Example

32-byte memory and 4-byte pages

(n=2 and m=4)
Using a page size of 4 bytes and a physical
memory of 32 bytes (8 pages).
Logical address 0 is page 0, offset 0.
Page 0 is in frame 5.
Logical address 0 maps to physical address 20 [=
(5 × 4) + 0].
Logical address 3 (page 0, offset 3) maps to
physical address 23 [= (5 × 4) + 3].
Logical address 4 is page 1, offset 0; according to
the page table, page 1 is mapped to frame 6.
Thus, logical address 4 maps to physical address
24 [= (6× 4) + 0].
Logical address 13 maps to physical address 9.

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 Free Frames

Before allocation After allocation

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 Implementation of Page Table
Page table is kept in main memory
Page-table base register (PTBR) points to the page table
Page-table length register (PTLR) indicates size of the page
table
In this scheme every data/instruction access requires two
memory accesses
One for the page table and one for the data / instruction
The two memory access problem can be solved by the
use of a special fast-lookup hardware cache called
associative memory or translation look-aside buffers
(TLBs)

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 Implementation of Page Table (Cont.)
Some TLBs store address-space identifiers (ASIDs) in each
TLB entry – uniquely identifies each process to provide
address-space protection for that process
Otherwise need to flush at every context switch
TLBs typically small (64 to 1,024 entries)
On a TLB miss, value is loaded into the TLB for faster access
next time
Replacement policies must be considered
Some entries can be wired down for permanent fast
access

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Paging Hardware With TLB

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 Background

Bus width 32 bits

Addressable memory bytes = 2^32
Allow each process to allocate all memory
Each process can have 2^32 ≈ 4 GB

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 Background
Create a page table for each process
PTBR (page table base register)
Points to the start of that table (is a pointer)
PTLR (page table length register)
Tells how many entries are there in that register
Each PCB has values for PTBR and PTLR
OS manages the place to store page table (PTBR value)
PTLR is not fixed → virtual addresses are not fixed
Virtual address has 4GB upper limit
Rarely a process needs all the 4 GBs
Add more entries when more memory is needed
Delete entries when the memory is freed.

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Two-Level Page-Table Scheme

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 Benefits
The page table itself need not be allocated
contiguously
The inner page tables can be allocated at different places
At times the inner page tables themselves can also be
stored into the backing store
Protection and security is also improved
A user cannot traverse all the page table entries by adding
or subtracting the pointer to inner page table entry
They become much more relevant in case of 64 bit
computers
64 bit computers provide 2^64 bytes of memory to each
process

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Memory Management

NUMERICALS

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 Paging – Effective Access Time
Find the effective access time when there is an 80% chance of a
TLB hit and it takes 100 nanosecond to access the memory.

EAT = Effective Access Time =

(tlb_hit_ratio x memory access time) +

(tlb_miss_ratio x 2*memory_access_time)

= (0.80 x 100) + (0.20 x 200) = 120 nanoseconds

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 Memory management – Memory size

Suppose you have a ram of size 32MB, calculate the total number
of locations/entries in ram and the number of bits required to
address each location.

Solution: Supposing the system is byte addressable.

Memory size = 32MB = loc x 1B (where loc is the number of
locations available in memory supposing each location is of 1 byte)
loc = 32MB/1B = 32M locations = 32 x 220 = 25 x 220
loc
(we divide memory size by the size of each location to get # of locations)
= 225
So the total number of bits required to represent 225 locations is = 25
Note: You maybe provided with the size of each location i.e. 1B assumed here.
Systems can be byte or word addressable in general.

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 Memory management - Paging
Supposing logical address = 26 bits
m – logical address
Physical address = 16 bits
Page size = 1KB
Find the following: # of frames & pages

x – physical address

Supposing system is Byte addressable. Now consider the following calculations:

Since the page size is 1KB. So, 1KB = 210 B ➔ 1024 locations
So the offset n = 10 bits.
Since x is the physical address space, and n is number of offset bits. x – n = physical address location
bits. 16 bits – 10 bits = 6 bits. Hence, 26 is the total number of frames.

m is the logical address space. As n = 10, m – n = 26 – 10 = 16. Hence 216 = 64K pages in the virtual
address space

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 Memory management - paging
Consider a logical address space of 64 pages of 1024 words each,
mapped onto a physical memory of 32 frames.
a. How many bits are required to represent the logical address space?
b. How many bits are there in the physical address?
Logical address space bits = m = ?
Recall that the size of the page/frame is = 2n and the size of logical address space are 2m
Then, logical address space = # of pages x page size
➔ 2m = # of pages x 2n
➔ 2m – n = # of pages
n=?
Page size = 2n ➔ 1024 = 2n
210 = 2n ➔ n = 10-bits
Again: # of pages = 2m-n ➔ 64 = 2m - 10 ➔ 26 = 2m - 10 ➔ 6 = m -10 ➔ m = 16-bits (logical
address)
Physical address: Let x be the physical address bits.
Size of physical address space = 2x
Size of physical address space = # of frames × frame size (frame size = page size )
Size of physical address space = 32 × 1024 ➔ 2x = 25 × 210 ➔ 2x = 215 ➔ number of bits = x =15
bits

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 Memory management - paging
Consider a logical address space of 64 pages of 1024 words each,
mapped onto a physical memory of 32 frames.
a. How many bits are required to represent the logical address space?
b. How many bits are there in the physical address?

Easy solution
Addressing within a 1024-words page requires 10 bits because 1024 = 210. Since
the logical address space consists of 64 pages = 26 pages, the logical addresses
must be 10+6 = 16 bits. Similarly, since there are 32 frame = 25 physical frames,
physical addresses are 5 + 10 = 15 bits long.

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 Memory management - paging
Consider a system using Paging for memory management. The
system uses a page size of 1024 bytes, and the length of the
address register is 18 bits. Now compute the following
parameters:

a) Size of RAM
b) Total number of frames in the RAM
c) Number of bits in a page table entry

Solution:

a) 218 = 28 * 210 = 256 * 1024 = 256 KB

b) 256 KB / 1024 B = 256

c) 18 - 10 = 8 bits

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 Memory management - Paging
Question
Write a C/C++ function to perform address translation in a system using Paging for
memory management. You are given with the page size, page table, and a logical block
no, and you are required to compute the corresponding physical address. Use the following
named constant, and the function prototype:
const int PS = ... ; // page size

int translate(int log, // logical block no

int tbl[], // page table
int n); // length of the page table

Solution:

int translate(int log, int tbl[], int n) {

int page = log / PS; // compute page no

int frame = tbl[page]; // get frame no
int off = log % PS; // calculate offset within the page

return frame * PS + off; // compute the physical address

}

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 Memory management - Paging

Consider a system with a page size of 256. Assume a process running in this system
has the following page table:
Page number Frame number

0 50

1 10

2 90

Now translate the following logical addresses into the corresponding paging physical
addresses:

i) 700

page = 700 / 256 = 2

frame = tbl[2] = 90

offset = 700 mod 256 = 188

phy add = 90 * 256 + 188

= 23,228
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Memory translation – logical to physical
Given a logical address of 2486 and a page size of 256. What is the corresponding
physical address?

We can divide the address by page size to get page #. So 2486/256 = 9.7
Therefore, the page # is 9. In the page table, we can grab the corresponding frame
number.

In order to find the offset, we take the mod of 2486 with 256. So, 2486%256 = 182

How to find the exact address?

Supposing that the page table returned 5 as the frame number against the page
number 9. The exact memory address of the frame will be:
(locations/entries_Per_Page*frame_Number)-1 (-1 because memory indexing starts
at 0)

So ➔ (256 * 5) – 1 = 1279
Now, we will add the offset to it to get the actual physical memory address: 1279 +
182 = 1461 = 0x5B5 is the memory location.

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 Memory translation – logical to physical(2nd method)
Given a logical address of 2486 and a page size of 256. What is the corresponding physical address?

Convert the logical address to binary number. 2486 in binary is: 100110110110
Now, take the log2 of the page size. i.e. log2 (256) = log2 (28) ➔ 8
offset

In the above binary number, the least-significant 8 numbers are the page offset. i.e. 1001 10110110
The underlined 0’s and 1’s is the offset. 10110110 = 182

The most significant left most 4 bits represents the page number.
page number

Page number is therefore 9.

How to find the exact address?

Supposing that the page table returned 5 as the frame number against the page number 9. The exact memory
address of the frame will be: (locations/entries_Per_Page*frame_Number)-1 (-1 because memory indexing
starts at 0)

So ➔ (256 * 5) – 1 = 1279
Now, we will add the offset to it to get the actual physical memory address: 1279 + 182 = 1461 = 0x5B5
Is the memory location.

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 Paging guidance

Paging arithmetic laws:

Page size = frame size

Logical address space (/size) = 2m
Logical address space (/size) = # of pages × page size
Physical address space (/size) = 2x (where x is the number of bits in physical address)
Physical address space (/size) = # of frames × frame size
Page size= frame size= 2n
# of pages= 2m-n
# of entries (records)in page table = # of pages

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