WEEK-2, DISCUSSION – 340 Lab:

Week-2 in the 340 Lab focuses on creating a tutorial that talks about building
gates in Verilog programming. It then asks us to test it.

ANSWER:

In the most basic terms, here are a few steps to create our modules, and
test the functional code.

STEP-1: Select desired family, device package and language.

STEP-1: Create a Verilog module. That involves your already created

project, then selecting the new source. You will then need to select
Verilog Module and click-to-add your project. The next sub-step is to
appropriately name your project then hit next.

Of note: any output/inputs are chosen to identify ports for your

module. This approach will enable a simple module code. It will
contain output and inputs for your gate.

STEP-3: Create a test fixture. That means right-click the module,

select the new source, and choose the text fixture (Verilog).

Of note: when you hit next, the available sources pop-up. Please
select the desired source for your text fixture. Hit finish.

STEP-4: In this step, please note that a video distills the process into
code. It is not clear as to the justification or rationale for the code.
Please research or query the meaning of the following symbols: %,#,d
$monitor, and symbols. It is a bit confusing or underwhelming to use
commands without a clear understanding as to why.

One improvement area: The video’s instructor could offer better

insight—to include, explaining things that translate to something more
meaningful (i.e., explaining that “req” means a variable in Verilog).
That might mean an “reg x” bit or a vector “reg(7:0) q;”

In terms of a wire data type in a Verilog description, it reflects the

physical wires. That is represented by “Wire gateoutput.”
With that, a wire enables gate-level instantiations and module
instantiations.

The Unit Under Test represented by “uut” notation show the gate for
testing the code, along with any outputs and inputs. It is unclear as to
why it is listed as “.il(il)”. Perhaps it is an abbreviated version of a
longer meaning.

Of note: The instructions of “initial begin” will set the value for each
input.

Note-2: If you have a listing of “#100”, that means to expect a delay

of 100 ns for global reset. However, in line 53, you will might see
“ #50 i1=1,” . That shows to wait for 50ns and then set i1 to 1 and
then for each input.

It is unclear as to why the instructor(s) are using an arithmetic operator

such as: ” % “ or “d” or “ $.”

Best,
Dan