Stagg It is a flop A is a Bi stale component that means

flip

A is used to hold 1 bit of Information either o or L

the exceptional antition operation there is

Do store of any is Called
in the pound

a need of extra storage sequised

Programstatuscard

Psw

are dassfied into types

flag
1 Conditional flag

4 Control flag

1 Conditimatlag flag 34 zero flag

i
carry 5 Sign flag
Auxiliaryflag

2

G flag
overflow
Pwgpay

3

panty
usigned Asthmatic amputation

It will be used in

1

Carrigg condition

to indicate the range of

ex 1 0101
to 10
cy o toff Cy L

LOL
o

I ILL

the lower nibble

there is an extra bit from

2
Auxillay tag If position

3rdPosition Sfo Higher nibble um

4 bit set else
is
quibbles

if it is true then Auxiliary Cary

reset

it is M

synIt on

LOLO Ax L

ex

O LO O
ne

D I I1 AX L

ex Lo Lo Lo Lo

to lo O l l l

01

Parity

Pa

It is set only when even no ones in the HP

3
Priya

1010 Lolo

ex O O

I 10 I

P 0 2 OL O P L

OLLI

Zero All zero

4 2ew as It is set only when 01PM

1000

ex
I 1010 2000

1 10 I 2 0 T

O 000

i 0 ILL

2 1

noir re
MSB bit is 1 then

5
Sign flag y if
no is 1 ve

if MSB bit in 0 then

MSB bit is L

Bt is set only

A is sent my
MsBbi

D 1001

ex 00

MSB

ve S L

signed Asthmetic computation

0VERHow Jt is used in
into the MSD S no carry

Then in a Camry
out the MSB or vice versa

y it is set else reset

it is true then

It

BE

1515 or 15
y

MSB

Reset o

set L

w
x I
 Eo so

Elsie DDgiso

L LOL 0 lol 001

0001

rest

of

Arithmetic

2S complement to perform the

consider the following

what is the status

JAHAN g L

27 O

so

1020001
t

Q-2 A processor that has carry, over ow and sign ag bits as part of its program status word
(PSW) performs addition of the following two 2's complement numbers 01001101 and 11101001.

ee
After the execution of this addition operation, the status of the carry, over ow and sign ags,
respectively will be : 

(A) 1,1,0 (B) 1,0,0 (C) 0,1,0 (D) 1,0,1 

f
Dl Il 0611101

1110100 0,0110110

note

o
 Oj on the 25 Complement Addition o veybw.es
Addition
whenever there is a from sign bit
9 flagged carry
Cannot occur when Tevaluemaddedtotheive
value
bit S previous bit
c Is flagged when Cary from signed

mapped flt
ther
d none
y jooo
o

110L
control flag the ALU
2 Contretflagy Based on the statusof
is controlled
execution Sequence

H Trap fly
Interrupt flag
3 Directionflag
executia
is set them is Singh step
when tap flag executi
1
Trap Has is reset their isn
program
When beepflag Complete

operation
set when Auto decmert
Direction It
is
2
it is reset when Auto
performed
performed
inoresunert operation

when interrupt occur

3 IntroptAggy a Jt is enabled
interrupt does not odor
disable when
 innit
w

a.ir aoT LOST

Physical Add

cpycImm.Regest mm
OI.aziAD

n i i

1Block 121

level L

n.er.la CLKB CLGMB 716GB LB

Size
SRAM DRAM Magnetic Disk
Inplementin Multipart
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Mw OS OS
Manageby campier
 D simullenousnecessMemoyorganizat

HIT D D D
adept
me if
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iii
TAvg hiT niht tH Crh4b

hitRaho NoJh TO
Totalnogat TT
go

5timesfaster
a In a 2
left memory organization Memory is
than herd 2 S Access time is tons less than Avg Access
Access time be 20ns what is the hit Ratio
time Let 4
a 00875 b o T C z T d L 75

ST TL
Tl Tay Lo
30ns
I Tze Loons Targ

Targ h T t l h HzTz
30 2,201 4 412 4 10.8ft
1002
Consider a system with 2 level cache. Access times of Level 1 cache, Level 2 cache and main
memory are 1ns, 10ns and 500ns, respectively. The hit rates of level 1 and level 2 caches are 0.8
and 0.9 respectively. What is the average access time of the system ignoring the search time
within the cache? 

(A) 13.0ns (B) 12.8ns (C) 12.6ns (D) 12.4ns 


T t I 41
Targ I l h
HIzt i
421,4035

L
Tl L 1 2 10 13 500
h O 8 Hz 09 434

hierarchical Access Memory

org r

DTD

In
hit huh Ms13 HnTy

La FAVS HIT 1 I hi hz Titty 1 I 4 1 42 Hs TtTztT

d 3 level memory has followig specification

not amiable in L then transfer it from

i7
to L
LoonsXY a 400

f referred block is
available in 12 then transfer it from toLz'S 4102
if not
it
how much time is required to Access
Tang MIT I hi H2 ITI t thi l th hz T 1kt T
s

I
Which of the following is not a form of memory ?

(A) instruction cache (B) instruction register

(C) instruction opcode (D) translation lookaside buffer 

1 43
051