3.

13 ON-CHIP MEMORY
perform-
considerable amount of on-chip memory to aid in system
The C5X architecture contains a

ance and integration:

Program Read-Only Memory
(ROM)
RAM (DARAM)
Data/Program Dual-Access
RAM (SARAM)
Data/Program Single-Access
 Architecture of TMS320C5X
63

(The 'C5X has a total address range of 224Kwords x 16 bits. The memory space is divided into ou
individually selectable 1memory segments: 64K-word program nory space, 64K-word local data
memory space, 64K-word i/O ports and 32K-word global data memory space.
3.13.1 Program ROM
All CSX DSPs carry a 16-bit on-chip maskable programmable ROM (sece Fig. 3.1 forsizes). Some of
the 'C5X DSPs have boot loader code resident in the on-chip ROM, and the other 'C5X DSPs ofter tne
boot loader code as an option. This memory is used for booting program code from slower extermal
ROM or EPROM to fast on-chip or external RAM. Once the custom program has been booted into
RAM, the boot ROM space can be removed from program memory space by setting the MP/MC bitin
the processor mode status register (PMST). The on-chip ROM is selected at reset by driving theMP
MC pin low. If the on-chip ROM is not selected, the 'C5X devices start execution from ofl-chip
memory.

3.13.2 Data/Program Dual-Access RAM

The DARAM is
All 'CSX DSPs carry a 1056-word X 16-bit on-chip dual-access RAM (DARAM).
DARAM block
divided into three individually selectable memory blocks: 512-word data or program
block B2. The DARAM is primarily
B0, 512-word data DARAM block Bl and 32-word data DARAM
as well. DARAM blocks
intended to store data values but, when needed, can be used to store programs
DARAM block BO can be configured by
B1 and B2 are always configured as data memory; however,
software as data or program memory.
The CPU operates with a 4-deep pipe-
DARAM improves the operational speed of the 'C5X CPU. Hence,
third stage and writes data on the fourth stage.
line. In this pipeline, the CPU reads data on the time the first
instruction sequence, the second instruction could be reading data at the same
for a given from and write to
and DAB) allow the CPU to read
instruction is writing data. The dual data buses (DB
DARAM in the same machine cycle.

RAM
3.13.3 Data/Program Single-Access 1-
of sizes varying from
Almost all 'CSX DSPs carry a
16-bit on-chip single-access RAM (SARAM)
executed at full speed once it is
Code be booted from an off-chip ROM and then
9Kx 16 words. can
software as data memory, as
SARAM. The SARAM can be configured by
loaded into the on-chip memory. The
SARAM is divided
or combination of both data memory and program
program memory 'CSX CPUs support parallel
blocks contiguous in address memory space. All
into 1K-and/or 2K-word can be accessed only
once per ma-
blocks. However, one SARAM block
accesses to these SARAM while accessing
write to one SARAM block
In other words, the CPU can read from or
chine cycle.
another SARAM block.

Protection
3.13.4 On-Chip Memory memories. When the
maskable option that protects
the contents of on-chip
The 'C5X DSPs have a spaces.
instruction can access the on-chip memory
related bit is set, no externally originating
 64 Deita/ Sgma Pxesson

3.14 ON-CHIP PERIPHERALS

have different on-chip peripherals c o e
stracture: however, they
A CSN DSPs have the sane CPU available are as folloa
penipherals
her
CPls The CSN DSP oa-chip
Ckock Generstor
Hardware Imer
Software-Programmable Wait-State Generators
Paraliel 1O Ports
Hos Port Interface (HPT)
Serial Port
Buffered Senial Port (BSP
Time-Division Multiplexed (TDM Serial Port
User-Maskable Ini.mupts

3.14.1 Clock Generator

phaselockedloop (PLL) circuit. The clo
of an internal oscillator andcircut
a
ihe clock generator consists a clock sogre
or driven externally by
generator can be driven internally by a crystal resonator the clock source by a specifc
ibe PLL circuit can generate an internal CPU clock by multiply1ng
that of the CPU can be used
actor and so a ciock source with a frequency lower than

3.14.2 Hardware Timer

available. This programmable timer clocks at a rate
A l6-bit hardware timer with a 4-bit prescaler is the imer's
that is betaween 12 and 1/32 of machine cycle rate (CLKOUTI), depending upon
the
reset or disabled by specif+c
status bits. Three
divide-down ratio. The timer can be stopped, restarted,
current count of the
timer counter register (TIM) gives the
registers control and operate the timer. The
for the timer. The 16-bit timer contro!
timer. The timer period register (PRD) defines the period
register (TCR) controls the operations of the timer.

Wait-State Generators
3.14.3 Software-Programmable
Software-programmable wait-state logic is incorporated in 'C5X DSPs allowing wait-state generation
hardware for
without any external with slower off-chip memory and IO devices. This
interfacing
feature consists of mutiple wait-state generating circuits. Each circuit is user-programmable to oper.
ate in different wait states for off-chip memory accesses.

3.14.4 Parallel 1/0 Ports

A total of 64K I10 ports are available. 16 of these ports are memory-mapped in data memory space.
Each of the L0 ports can be addressed by the IN or the OUT instruction. The memory-mapped 10
ports can be accessed with any instruction that reads from or writes to data memory. The IS signal
indicates a read or write operation through an 10 port. The 'CSX can easily interface with extenal I
O devices through the 10 ports while requiring minimal of-chip address decoding circuits.
 Architecture of TMS32OCSX 65

3.14.5 Host Port Interface (HPI)

The HPI is available on the CS7S and LC57. It is an 8-bit parallel 1/0 port that provides an intertace to
a host processor. Intomation is exchanged between the DSP and the host processor through on-Chip
memory that is accessible to both the host processor and the 'C57.

3.14.6 Serial Port

Three diterent kinds of serial ports are available: a general-purpose serial port, a time-division
multiplexed (TDM) serial port and a buffered serial port (BSP). Each C5X contains at least one
general-purpose, high-speed synchronous, full-duplexed serial port interface that provides direct com-
nunication with serial devices such as codecs, serial analog-to-digital (A/D) converters and other
mu

serial systems. The serial port is capable of operating at up to one-fourth the machine cycle rate
(CLKOUT). The serial port transmitter and receiver are double-buffered and individually controlled
by maskable external interupt signals. Data is framed either as bytes or as words.
Five 16-bit registers (SPC, DRR, DXR, XSR, RSR) control and operate the serial port interface.
The serial port control (SPC) register contains the mode control and status bits of the serial port. The
data receive register (DRR) holds the incoming serial data, and the data transmit register (DXR) holds
the outgoing serial data. The data transmit shift register (XSR) controls the shifting of the data from
the DXR to the output pin. The data receive shift register (RSR) controls the storing of the data from
the input pin to the DRR.

3.14.7 Buffered Serial Port (BSP)

The BSP is available on the'C56 and 'C57 devices. It is a full-duplexed, double-buffered serial port and
an autobuffering unit (ABU). The BSP provides flexibility on the data stream length. The ABU supports
data transfer and reduces interrupt latencies. The BSP has a 2K-word buffer, which
re-
high-speed
sides in the C5X internal memory. Five BSP registers control and operate the BSP.

3.14.8 TDM Serial Port

serial port that can
The TDM serial port available on the 'C50, '"C51 and 'C53 devices is a full-duplexed
time-division multiplexed opera-
be configured by software either for synchronous operations or for
tions. The TDM serial port is commonly used in multiprocessor applications.

3.14.9 User-Maskable Interrupts

five internal interrupts, a timer interrupt and four serial
Fourextermal interrupt lines (INT1-INT4) and contents of
When an interrupt service routine (ISR) is executed, the
port interrupts are user maskable.
hardware stack, and the contents of 11 specific CPUU
the program counter are saved on an 8-level
registers, ACC, ACCB, PREG, ST0, ST1, PMST, TREGO, TREGI, TREG2, INDX and ARCR, are
saved in one deep stack (shadow registers). When a return from interrupt instruction is executed, the
CPU registers' contents are restored.