Memory Organization

Module 5
 Main memory
 Auxillary memory
 Cache memory
 RAM
 ROM
 Bootst rap Loader
Primary Memory
 Primary memory is internal memory of the computer.
 Memory unit that directly communicate with CPU.
 It is also known as main memory or Temporary memory.
 Primary Memory holds the data and instruction on which computer
is currently working.
 Primary Memory is volatile in nature.
 It means when power is switched off it lost all data.

Secondary Memory
 Secondary Memory is external memory of the computer.
 It is also known as Auxiliary memory and permanent memory.
 It is used to store the different programs and the information permanently.
 Secondary Memory is non volatile in nature.
Main Memory
The principal technology used for the main memory is based on semiconductor
integrated circuits.

Main memory can be generally classified into 2:

1. Random-access memory (RAM)
2. Read-only memory (ROM).
 RAM
 It stands for Random Access Memory.
 RAM is known as read /write memory.
 It is a temporary memory.
 The information stored in this memory is lost as the power supply to the computer is
switched off. That’s why RAM is also called “Volatile Memory”
Types of RAM
 Static RAM
Static RAM also known as SRAM.
The static RAM consists essentially of internal flip-flops that store the binary information.
The stored information remains valid as long as power is applied to the unit.
SRAM are of higher cost and consume more power.
They have higher speed than Dynamic RAM

 Dynamic RAM
Dynamic RAM also known as DRAM.
The dynamic RAM stores the binary information in the form of electric charges that are applied
to capacitors.
The capacitors are provided inside the chip by MOS transistors.
Dram requires an external memory refresh circuit which periodically rewrites the data in
the capacitors.
Retain data for a few seconds if the power is lost.
ROM (Read Only Memory)
ROM is a Permanent Type memory.
ROM is used for storing programs that are permanently resident in the computer.
Its content are not lost when power supply is switched off.

Content of ROM is decided by the computer manufacturer and permanently stored

at the time of manufacturing.

ROM cannot be overwritten by the computer.

It is also called “Non-Volatile Memory”.
 Computer Starts up

Among other things, the ROM portion of main memory is needed for storing an
initial program called a bootstrap loader.
The bootstrap loader is a program whose function is to start the computer
software operating when power is turned on.
The contents of ROM remain unchanged after power is turned off and on again.

 When power is turned on, the hardware of the computer sets the program
counter to the first address of the bootstrap loader.
 The bootstrap program loads a portion of the operating system from disk to
main memory and control is then transferred to the operating system, which
prepares the computer for general use
RAM Chip
RAM Chip

 A RAM chip is better suited for communication with the CPU if it has one or
more control inputs that select the chip only when needed.
 Another common feature is a bidirectional data bus that allows the transfer
of data either from memory to CPU during a read operation, or from CPU to
memory during a write operation.
 A bidirectional bus can be constructed with three-state buffers.
 A three-state buffer output can be placed in one of three possible states
 a signal equivalent to logic 1
 a signal equivalent to logic 0
 a highimpedance state.

The logic 1 and 0 are normal digital signals.

The high impedance state behaves like an open circuit, which means that the output
does not carry a signal and has no logic significance.
ROM Chip
 A ROM chip is organized externally in a similar manner. However, since a ROM
can only read, the data bus can only be in an output mode.

 For the same-size chip, it is possible to have more bits of ROM than of RAM
because the internal binary cells in ROM occupy less space than in RAM.
For this reason, the diagram specifies a 512-byte ROM, while the RAM has only
128 bytes.

 The nine address lines in the ROM chip specify any one of the 512 bytes stored
in it.
 The two chip select inputs must be CS1 = 1 and CS2 = 0 for the unit to operate.
Otherwise, the data bus is in a high-impedance state.
Memory Connection to CPU
 RAM and ROM chips are connected to a CPU through the data and address
buses.
 The low-order lines in the address bus select the byte within the chips and
other lines in the address bus select a particular chip through its chip select
inputs.
 Each RAM receives the seven low-order bits of the address bus to select one of
128 possible bytes.
 The particular RAM chip selected is determined from lines 8 and 9 in the
address bus. This is done through a 2 x 4 decoder whose outputs go to the CS1
inputs in each RAM chip.
Thus, when address lines 8 and 9 are equal to 00, the first RAM chip is
selected. When 01, the second RAM chip is selected, and so on.
 The RD and WR outputs from the microprocessor are applied to the inputs of
each RAM chip.
 The selection between RAM and ROM is achieved through bus line 10. The
RAMs are selected when the bit in this line is 0, and the ROM when the bit is 1.
 The other chip select input in the ROM is connected to the RD control line for
the ROM chip to be enabled only during a read operation.
 Address bus lines 1 to 9 are applied to the input address of ROM without going
through the decoder.
 This assigns addresses 0 to 511 to RAM and 512 to 1023 to ROM.
 The data bus of the ROM has only an output capability, whereas the data bus
connected to the RAMs can transfer information in both directions
Auxillary Storage Device
 Magnetic disc – FDD, HDD
 Magnetic tape –Backup/ Program
 Optical Disk –CDR, ODD, DVD

 The important characteristics:

 access mode
 access time
 transfer rate
 Capacity
 cost
 Access time - the average time required to reach a storage location in memory
and obtain its contents.
 In electromechanical devices Access Time= Seek Time + Transfer Time
 seek time - Time required to position the read-write head to a location.
 Transfer time – Time required to transfer data to or from the device.
 Magnetic Disk / Drums
Magnetic Tape

 Magnetic tape data storage is a system for storing digital information on

magnetic tape using digital recording.

 Magnetic tape is a medium for magnetic recording, made of a thin,

magnetizable coating on a long, narrow strip of plastic film.

 A device that stores computer data on magnetic tape is known as a tape drive
 Stored data can be identified for access by the content of the data itself rather
than by an address.
 A memory unit accessed by content is called an associative memory or content
addressable memory (CAM).
One cell of Associative Memory
Tag bit
 If unwanted words have to be deleted and new words inserted one at a time,
there is a need for a special register (tag register) to distinguish between
active and inactive words.
 A tag register would have as many bits as there are words in the memory.
 For every active word stored in memory, the corresponding bit in the tag
register is set to 1.
 A word is deleted from memory by clearing its tag bit to 0.
 Words are stored in memory by scanning the tag register until the first 0 bit is
encountered. This gives the first available inactive word and a position for
writing a new word.
Cache Memory
 Locality of Reference
 The references to memory tend to be confined within a few localized
areas in memory.
 A fast small memory
 keeping the most frequently accessed instructions and data in the
fast cache memory

Hit Ratio
 hit : the CPU finds the word in the cache
 miss : the word is not found in cache
Hit ratio = percentage of memory accesses satisfied by the cache.
Writing to Cache
Cache Replacement Algorithm

1. FIFO (First-In First-Out)

2. LRU (Least Recently Used)
3. LFU (Least Frequently Used)
4. Random Replacement
Mapping
 The transformation of data from main memory to cache memory is referred
to as a mapping process.
 Types of mapping
 Associative mapping
 Direct mapping
 Set-associative mapping
Associative mapping
 fastest and most flexible cache organization
 The associative memory stores both the address and content (data) of the
memory word.
 This permits any location in cache to store any word from main memory.
Direct Mapping
Direct mapping with blocks

Disadvantage of Direct mapping - two words with the same index in

their address but with different tag values cannot reside in cache
memory at the same time.
 Set-associative mapping
 Each word of cache can store two or more words of memory under the same
index address.
 Each data word is stored together with its tag and the number of tag-data
items in one word of cache is said to form a set.

When the CPU generates a memory request, the index value of the address is used
to access the cache. The tag field of the CPU address is compared with both tags in
the cache to determine if a match occurs.
Cache initialization
Cache is initialized.
1) when power is applied to the computer
2) when main memory is loaded with a complete set of programs from
auxiliary memory
valid bit
indicate whether or not the word contains valid data

 After initialization the cache is considered to be empty, but in effect it contains some nonvalid data.
 With each word in cache a valid bit is there to indicate whether or not the word contains valid data.
 The cache is initialized by clearing all the valid bits to 0.
 The valid bit of a particular cache word is set to 1 the first time this word is loaded from main
memory and stays set unless the cache has to be initialized again.
Virtual Memory
 Virtual memory is a concept used in some large computer systems that permit
the user to construct programs as though a large memory space were
available, equal to the totality of auxiliary memory.
 An address used by a programmer will be called a virtual address.
 The set of such addresses gives an address space.
 An address in main memory is called a location or physical address.
 The set of such locations is called the memory space.
Address Mapping Using Pages
Page(Block) Replacement
Page Fault : the page referenced by the CPU is not in main memory
 a new page should be transferred from auxiliary memory to main memory
Replacement algorithm :
Random Replacement
First In First Out (FIFO)
Last In First Out (LIFO)
Least Recently Used (LRU)
Most Frequently Used (MFU)
Optimal Page Replacement

Belady's anomaly: Generally if we increase the number of frames in the

memory, the number of page faults should decrease due to obvious
reasons. Belady’s anomaly refers to the phenomena where increasing
the number of frames in memory, increases the page faults as well.
 Memory Management Hardware
 Multiprogramming
 Basic components of a Memory Management Unit
 1) Address mapping
 2) Common program sharing
 3) Program protection
 Logical address
Segment Page Word

Segment table Page table

Block Word
Physical address
(a) Logical to physical address mapping

Argument register

Segment Page Block

(b) Associative memory translation look-aside buffer (TLB)

Translation Look Aside Buffer (TLB)

 A Translation look aside buffer can be defined as a memory cache which can
be used to reduce the time taken to access the page table again and again.

 It is a memory cache which is closer to the CPU and the time taken by CPU to
access TLB is lesser then that taken to access main memory.
 TLB follows the concept of locality of reference which means that it contains
only the entries of those many pages that are frequently accessed by the CPU
Memory Protection
Base address Length Protection

Typical segment descriptor :

Access Rights : protecting the programs residing in memory

1) Full read and write privileges : no protection
2) Read only : write protection
3) Execute only : program protection
4) System only : operating system protection
Input Output Organization
 Provides an efficient mode of communication between the central system and the outside
environment
Peripheral (or I/O Device)
Input or Output devices attached to the computer
 Monitor (Visual Output Device) : CRT, LCD
 Printer (Hard Copy Device) : Dot matrix (impact), thermal, ink jet, laser (non-impact)

Input-Output Interface

 Conversion of signal values may be

required

 Synchronization mechanism may be

needed (The data transfer rate of
peripherals is usually slower than the
transfer rate of the CPU)

Data codes and formats in peripherals differ from the word format in
the CPU and Memory .
The operating modes of peripherals are different from each other
 Each peripherals must be controlled so as not to disturb the operation of other peripherals
connected to theCPU
I/O Bus and Interface Modules
Data Transfer

Synchronous Data Transfer

 All data transfers occur simultaneously during the occurrence of a clock pulse.
 Registers in the interface share a common clock with CPU registers

Asynchronous Data Transfer

 Internal timing in each unit (CPU and Interface) is independent
 Each unit uses its own private clock for internal registers
Strobe & Handshaking

• Strobe control: A strobe pulse is supplied by one unit to indicate to the other unit
when the transfer has to occur.

• Handshaking: This method is commonly used to accompany each data item being
transferred with a control signal that indicates data in the bus. The unit receiving the
data item responds with another signal to acknowledge receipt of the data.
The Strobe Control
 The Strobe Control method of asynchronous data transfer employs a single
control line to time each transfer.
 This control line is also known as a strobe, and it may be achieved either by
source or destination, depending on which initiate the transfer.
 2 Types:
 Source initiated Strobe
 Destination initiated Strobe
Source initiated strobe
 Source initiated Strobe - Strobe is initiated first by source
 The source unit first places the data on the data bus.
 After a brief delay to ensure that the data resolve to a stable value, the source activates
a strobe pulse.
 The information on the data bus and strobe control signal remains in the active state for
a sufficient time to allow the destination unit to receive the data.

 The destination unit uses a falling edge of strobe control to transfer the contents of a
data bus to one of its internal registers.
 The source removes the data from the data bus after it disables its strobe pulse. Thus,
new valid data will be available only after the strobe is enabled again.

 In this case, the strobe may be a memory-write control signal from the CPU to a
memory unit. The CPU places the word on the data bus and informs the memory unit,
which is the destination.
Destination initiated strobe
 The strobe initiated by destination
 The destination unit first activates the strobe pulse, informing the source to provide the
data.
 The source unit responds by placing the requested binary information on the data bus.
The data must be valid and remain on the bus long enough for the destination unit to
accept it.
 The falling edge of the strobe pulse can use again to trigger a destination register. The
destination unit then disables the strobe.
 Finally, and source removes the data from the data bus after a determined time interval.
 In this case, the strobe may be a memory read control from the CPU to a memory unit.
The CPU initiates the read operation to inform the memory, which is a source unit, to
place the selected word into the data bus.
Handshaking Method
 Disadvantages :
The source unit that initiates the transfer has no way of knowing whether the destination
has received the data that was placed in the bus. Similarly, a destination unit that initiates
the transfer has no way of knowing whether the source unit has placed data on the bus.
Modes of Transfer-Data transfer to and
from peripherals
 We store the binary information received through an external device in the memory
unit. The information transferred from the CPU to external devices originates from the
memory unit. Although the CPU processes the data, the target and source are always
the memory unit. We can transfer this information using three different modes of
transfer.
1. Programmed I/O
2. Interrupt- initiated I/O
3. Direct memory access( DMA)
Programmed I/O

 Programmed I/O uses the I/O instructions written in the computer program. The
instructions in the program initiate every data item transfer. Usually, the data transfer is
from a memory and CPU register. This case requires constant monitoring by the peripheral
device's CPU.
 Advantages:
• Programmed I/O is simple to implement.
• It requires very little hardware support.
• CPU checks status bits periodically.

Disadvantages:
• The processor has to wait for a long time for the I/O module to be ready for either
transmission or reception of data.
• The performance of the entire system is severely degraded.
Interrupt- initiated I/O

 The interrupt facilities and special commands inform the interface for issuing an
interrupt request signal as soon as the data is available from any device. In the
meantime, the CPU can execute other programs, and the interface will keep
monitoring the i/O device. Whenever it determines that the device is ready for
transferring data interface initiates an interrupt request signal to the CPU. As soon as
the CPU detects an external interrupt signal, it stops the program it was already
executing, branches to the service program to process the I/O transfer, and returns to
the program it was initially running.
Direct Memory Access

 Direct Memory Access (DMA) transfers the block of data between

the memory and peripheral devices of the system, without the
participation of the processor. The unit that controls the activity of
accessing memory directly is called a DMA controller.
 To speed up the transfer of data between I/O devices and memory, DMA
controller acts as station master. DMA controller transfers data with minimal
intervention of the processor.
Input/ Output Controllers