MEMORY

 Computer memory is the storage space in computer where data to be processed and the instructions
required for processing are stored.

 Memory is divided into large number of small parts called cells.

 Each location or cell has a unique address which varies from zero to memory size minus one.

 Memory is an essential element of a computing system.

 Classification

1. Internal Memory – Cache memory and Primary/Main memory

2. External Memory – Magnetic disk, Optical disk, Secondary memory

MEMORY HIERARCHY

As we move from top to

bottom:

 Capacity increases

 Cost per bit of storage

increases

 Frequency of access
of the memory by
CPU decreases

 Access time of CPU

increases
MEMORY DEVICES
 A memory device consists of a set of registers (memory locations) that share a common set of input
lines (input bus) and a common set of output lines (output bus).

 With Read/Write memory devices we can store (write) into or read from any memory location.

 We select which location to access by specifying its address on the address bus.

 We select a specific memory chip and specify a READ or a WRITE operation using control signals
(e.g. RD/WR) on the control bus.

 Time taken for the read data to appear at the device output after
specifying the location address is access time (ns).
CAPACITY OF A MEMORY DEVICE
 Storage Capacity: Number of storage locations x width of data in each location

With Address = n bits

Number of registers (storage locations) = 2n locations

If each location is m-bit wide, then memory capacity is 2n x m bits.

 Example: n = 10, m = 8

210 x 8 bits

1K Bytes of storage = 1 KB = 8 K bits

PRIMARY MEMORY
 Primary memory is classified as:

RAM

ROM
RANDOM ACCESS MEMORY
 RAM constitutes the internal memory of the CPU for storing data, program and program result.

 It is Read/Write memory.

 Access time is independent of the address location i.e. each memory location can be reached in the same time.

 RAM is very fast bot equally expensive.

 It is a volatile memory i.e. the data stored is lost when computer is switched off or there is a power failure. That is
the reason a UPS is always used with a computer.

 RAM is small, both in terms of physical size as well as the amount of data it can hold.

 RAMs are classified into

SRAM – Static RAM

DRAM – Dynamic RAM

STATIC RAM

 Each bit is stored in a latch or flip flop.

 Once data is written, it remains as long as power is ON.

 More costly, requires a larger number of transistors

 Lower storage capacity

 Faster access times

 SRAM is used a cache memory.

DYNAMIC RAM

 Each cell is composed of one capacitor and one transistor.

 Each bit is stored as a charge on a capacitor.

 The charge leaks, and data needs to be refreshed to prevent data loss (snag).

 Simpler circuit

 Larger storage capacity

 Lower cost

 Slower access time

DRAM vs SRAM
RAM
 Address

- Location in memory

- Must be decoded to select the appropriate information and read/write the associated data

- k-bit address , 2k memory locations

 Data

- Binary information of interest

- Stored in a specific location in memory

- Typically organized into words

- Each word has n bits

RAM

1024 locations. Address lines - 10

RAM
RAM – WRITE CYCLE
RAM – READ CYCLE
BASIC MEMORY CELL
4 X 4 RAM
READ ONLY MEMORY

 Memory from which we can only read and not write on it.

 Memory is written (programmed) only once.

 Reading from ROM is non destructive.

 Access time to read from any memory location is same.

 Non volatile – Information is retained even in case of power failure.

 ROM stores instructions required to start computer when power is first turned on (bootstrap).

 ROM chips are not only used in computers but also in other electronic items.
TYPES OF ROM
 MROM (Masked ROM)

Very first ROMs were hard wired devices, that contained a pre-programmed set od data or instructions.

 PROM (Programmable ROM)

Read-only memory, that can be modified only once by the user. Users buy a blank PROM, enter the contents using
a PROM programmer. It is non-erasable.

 EPROM (Erasable and Programmable ROM)

Can be erased by exposing it to UV light. Usually an EPROM eraser does this function.

 EEPROM (Electrically Erasable and Programmable ROM)

Programmed and erased electrically. Locations can be selectively erased or programmed. Erase one bit at a time
and not entire chip in one go, thus the reprogramming process is very slow.
 RAM – TIMING WAVEFORMS
 The CPU is generally synchronized with its own clock.

 Memory unit does not have a clock. The read and write operations are specified by the control inputs.

 Access time of a memory is the time required to select a word and read it.

 Cycle time of a memory is the time required to complete a write operation.

 Thus, the CPU must provide the memory control signals such that the read and write operations are
synchronized with the internal clock of CPU.

 Thus, the access time and cycle time of the memory are defined in terms of CPU clock cycles.

 Consider a CPU with a clock frequency of 50 MHz and a memory with access time and memory time ≈ 50 ns.

CPU clock time = 20 ns

RAM – WRITE CYCLE
20 ns
RAM – READ CYCLE
50 ns
4 X 4 RAM
COINCIDENT DECODING
 A decoder with k inputs and 2k outputs requires 2k AND gates with k inputs per gate.

 The total number of gates and the number of inputs per gate can be reduced by employing two decoders in a
two‐dimensional selection scheme.

 The basic idea in two‐dimensional decoding is to arrange the memory cells in an array that is close as possible
to a square.

 In this configuration, two k /2‐input decoders are used instead of one k ‐input decoder.

 One decoder performs the row selection and the other the column selection in a two‐dimensional matrix
configuration.
COINCIDENT DECODING FOR 1K WORD MEMORY
COINCIDENT DECODING FOR 1K MEMORY

 A 1K word memory is designed using two 5 X 32 decoders instead of 10 X 1024 decoders.

 Single decoder would require 1024 AND gates with 10 inputs each.

 Two decoders would need 64 AND gates with 5 inputs each.

 5 most significant bits of address go to input X and the 5 least significant bits go to input Y.

 Each word within the memory is selected by the coincidence of one X line and one Y line.

 Example – Consider word with address 404, 404 - 01100 10100

Thus X = 01100 and Y = 10100

ADDRESS MULTIPLEXING
 DRAMs typically have four times the density of SRAMs.

 This allows four times as much memory capacity to be placed on a given size of chip.

 Because of their large capacity, the address decoding of DRAMs is arranged in a two‐dimensional array, and
larger memories often have multiple arrays.

 To reduce the number of pins in the IC package, designers utilize address multiplexing whereby one set
of address input pins accommodates the address components.

 In a two‐dimensional array, the address is applied in two parts at different times, with the row address first and
the column address second.

 Since the same set of pins is used for both parts of the address, the size of the package is decreased
significantly.
ADDRESS MULTIPLEXING FOR 64K RAM
ROM CELLS
 ROM cells use the presence or absence of a transistor connection at a row/column junction to represent a 1 or
a 0.

 A PROM uses some type of fusing process to store bits, in which a memory link is burned open or left intact to
represent a 0 or a 1.
ROM BLOCK DIAGRAM
ROM EXAMPLE
ROM EXAMPLE
ROM EXAMPLE
ROM EXAMPLE
PROGRAMMABLE LOGIC DEVICES
 PLD is an integrated circuit with programmable gates divided into an AND array and an OR array to provide an
AND-OR sum of product implementation.

 The PLD‘s can be reprogrammed in few seconds and hence gives more flexibility to experiment with designs.

 Reprogramming feature of PLDs also makes it possible to accept changes/modifications in the previously
design circuits.

 The advantages of using programmable logic devices are:

- Reduced space requirements.

- Reduced power requirements.

- Compact circuitry.

- Low development cost.

- Higher switching speed.

FUNDAMENTAL PLDs
ARRAYS
 All PLDs consists of programmable arrays.

 A programmable array is essentially a grid of conductors that form rows and columns with a fusible link at
each cross point.

 Arrays can be either fixed or programmable.

OR Array

 It consists of an array of OR gates connected to a programmable matrix with fusible links at each cross point
of a row and column

AND Array

 This type of array consists of AND gates connected to a programmable matrix with fusible links at each cross
points
ARRAYS
PROGRAMMABLE LOGIC ARRAY
 The PLA is similar to the PROM in concept except that the PLA does not provide full coding of the variables
and does not generate all the minterms.

 The decoder is replaced by an array of AND gates that can be programmed to generate any product term of
the input variables.

 The product term are then connected to OR gates to provide the sum of products for the required Boolean
functions.

 The AND gates and OR gates inside the PLA are initially fabricated with fuses among them.

 The specific boolean functions are implemented in sum of products form by blowing the appropriate fuses and
leaving the desired connections.
EXAMPLE
EXAMPLE
EXAMPLE
EXAMPLE
EXAMPLE
EXAMPLE
EXAMPLE
EXAMPLE
EXAMPLE
EXAMPLE
PROGRAMMABLE ARRAY LOGIC
 The PAL is a programmable logic device with a fixed OR array and a programmable AND array.

 Because only the AND gates are programmable, the PAL is easier to program than, but is not as flexible as,
the PLA.

 Each input has a buffer–inverter gate, and each output is generated by a fixed OR gate.

 A typical four-input, four output PAL has four sections in the unit, each composed of an AND–OR array with
three programmable AND gates in each section and one fixed OR gate.

 In designing with a PAL, the Boolean functions must be simplified to fit into each section.

 Unlike the situation with a PLA, a product term cannot be shared among two or more OR gates.

 Therefore, each function can be simplified by itself, without regard to common product terms.

 The number of product terms in each section is fixed, and if the number of terms in the function is too large, it
may be necessary to use two sections to implement one Boolean function.
PROGRAMMABLE ARRAY LOGIC
EXAMPLE
EXAMPLE
EXAMPLE
EXAMPLE
SEQUENTIAL PROGRAMMABLE DEVICES
 Digital systems are designed with flip‐flops and gates.

 Since the combinational PLD consists of only gates, it is necessary to include external flip ‐flops when they are
used in the design.

 Sequential programmable devices include both gates and flip‐flops. In this way, the device can be programmed
to perform a variety of sequential‐circuit functions.

 There are three major types of sequential programming devices namely

1.Sequential (or simple) programmable logic device (SPLD)

2.Complex programmable logic device (CPLD)

3.Field‐programmable gate array (FPGA)

SEQUENTIAL PROGRAMMABLE LOGIC DEVICE (SPLD)
 The SPLD includes flip‐flops, in addition to the AND–OR array, within the integrated circuit chip.

 The circuit outputs can be taken from the OR gates or from the outputs of the flip ‐flops.

 The flip‐flops may be of the D or the JK type.

 The configuration mostly used in an SPLD is the combinational PAL together with D flip ‐flops.

 Each section of an SPLD is called a macrocell, which is a circuit that contains a sum ‐of ‐products combinational
logic function and a flip‐flop.

 The AND–OR array is the same as in the combinational PAL.

 The output is driven by an edge‐triggered D flip‐flop connected to a common clock input and changes state on
a clock edge.

 The output of the flip‐flop is fed back into one of the inputs of the programmable AND gates to provide the
present‐state condition for the sequential circuit.

 A typical SPLD has from 8 to 10 macrocells within one IC package.

SPLD BASIC MACRO CELL
COMPLEX PROGRAMMABLE LOGIC DEVICE (CPLD)
 The design of a digital system using PLDs often requires the connection of several devices to produce the
complete specification.

 For this type of application, it is more economical to use a complex programmable logic device (CPLD), which
is a collection of individual PLDs on a single integrated circuit.

 A programmable interconnection structure allows the PLDs to be connected to each other in the same way that
can be done with individual PLDs.

 The device consists of multiple PLDs interconnected through a programmable switch matrix.

 The switch matrix receives inputs from the I/O block and directs them to the individual macrocells. Similarly,
selected outputs from macrocells are sent to the outputs as needed.

 Each PLD typically contains from 8 to 16 macrocells.

GENERAL CPLD CONFIGURATION
FIELD PROGRAMMABLE GATE ARRAY (FPGA)

 A field‐programmable gate array (FPGA) is a VLSI circuit that can be programmed at the user’s location.

 A typical FPGA consists of

- array of millions of logic blocks

- programmable input and output blocks

- programmable interconnections
FIELD PROGRAMMABLE GATE ARRAY (FPGA)
 A typical FPGA logic block consists of lookup tables, multiplexers, gates, and flip ‐flops.

 A lookup table is a truth table stored in an SRAM and provides the combinational circuit functions for the logic
block.

 The combinational logic section, along with a number of programmable multiplexers, is used to configure the
input equations for the flip‐flop and the output of the logic block.

 The program can be downloaded either from a host computer or

from an onboard PROM.

 The program remains in SRAM until the FPGA is reprogrammed or

the power is turned off. The device must be reprogrammed every time
power is turned on.

 The ability to reprogram the FPGA can serve a variety of applications

by using different logic implementations in the program.