Memory

Memory
A collection of cells,
each with a unique
physical address;
Both addresses and
contents are in
binary

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 Memory
◼ The Memory stores the instructions as
well as data
◼ The CPU has to be directed to the
address of the instruction codes
◼ The memory is connected to the CPU
through the following lines:
1. Address
2. Data
3. Control
 Addressability
The Processor "sees" all the other parts of the computer,
(ROM & RAM, Backing storage, Input and Output devices)
as one continuous block of locations each with its own
unique address.

Each location has a different binary number which identifies it.

This is its address.

Giving every part of the computer a unique address allows

the processor to communicate easily with any other part of
the computer system and is known as addressability.
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 The three buses which carry signals around the computer
system each have their own particular function.

1. Address Bus
This is used by the Processor to indicate which location has
to be accessed.

It is a one-way bus from the processor as the processor

dictates all movement of signals.

The number of lines on the address bus determines the

maximum amount of memory locations which can be accessed.
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Address bus width and addressable memory 2 lines
A 2 line address bus would allow 4 addresses. 00
01
because 22 = 4. 10
11
A 3 line address bus would allow 8 addresses.
because 23 = 8. 3 lines
000
X lines on the address bus allows 2x addresses. 001
010
A 24 line address bus allows 011
224 = 16 777 216 addresses = 16Mega addresses. 100
101
A 32 line address bus allows 110
232 = 4Giga addresses. 111

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 Calculating maximum memory size

To calculate maximum memory size we need to consider two

elements:

the number of memory locations(addresses)

& the size of each memory location.

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 example:
Calculate the maximum memory size of a computer with a
24 bit address bus and a memory word size of 16 bits.

A 24 bit address bus allows 224 addresses = 16 Mega addresses.

Each address contains 16 bits = 2 Bytes

Maximum memory size =16 Mega x 2 Bytes = 32 MB

If the program memory of a microcontroller is of size

16KB and memory is organized into 16 bits for each
address, what is the minimum size of Program
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Counter required for such a device?
2. Data bus
This is the bus which is used to transfer the actual
data to and from the locations.
It is a two-way bus as data may be going to the processor
(Read) or coming from the processor(Write).

3. Control bus
The Control bus is a collective name for a number of discrete
lines each of which has a different function and operates at
different times. They are best viewed as a number of
individual lines.
Examples include: read line, write line, reset line, clock line,
interrupt line.

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 Memory Read
◼ In a memory read operation the CPU loads the
address onto the address bus.
◼ Most cases these lines are fed to a decoder
which selects the proper memory location.
◼ The CPU then sends a read control signal.
◼ The data stored in that location is transferred to
the processor via the data lines.
 Memory Write

◼ In a memory write operation the CPU loads the

address onto the address bus.
◼ The CPU copies the data onto the data bus.
◼ The CPU then activates the write line on the
control bus.
◼ The memory controller copies the data from the
data bus and puts it into the required memory
location.
 Memory Classification
◼ The memory can be classified in various
ways i.e. based on the location, power
consumption, way of data storage etc.
◼ The memory at the basic level can be
classified as:
1. Processor Memory (Register Array)
2. Internal on-chip memory
3. Cache memory
4. Primary memory
5. Secondary memory
 Processor memory
◼ These are the registers used to store the
operands and the result of an instruction.
◼ The more the registers the faster the
instruction execution.
◼ But the complexity of the architecture
puts a limit on the amount of the
processor memory.
 Internal on-chip Memory
◼ In some processors there may be a
block of memory location.
◼ They are treated in the same way as
the external memory.
◼ However it is very fast.
Primary Memory
◼ This is the one which sits just out side
the CPU.
◼ It can also stay in the same chip as of
CPU.
◼ These memories can be static or
dynamic.
Cache Memory
◼ This is situated in between the
processor and the primary memory.
◼ This serves as a buffer to the
immediate instructions or data which
the processor anticipates.
◼ There can be more than one levels of
cache memory.
 Secondary Memory
◼ These are generally treated as Input/Output
devices.
◼ They are much cheaper mass storage and slower
devices connected through some input/output
interface circuits.
◼ They are generally magnetic or optical memories
such as Hard Disk and CDROM devices.
 Memory can also be divided into
Volatile and Non-volatile memory.
Volatile Memory
◼ The contents are erased when the
power is switched off.
◼ Semiconductor Random Access
Memories fall into this category.
 Non-volatile Memory
◼ The contents are intact even if the power
is switched off.
◼ Magnetic Memories (Hard Disks), Optical
Disks (CDROMs), Read Only Memories
(ROM) fall under this category.
◼ Holds bits after power is no longer
supplied.
 Memory Specifications
The specification of a typical memory is as
follows :
◼ The storage capacity: The number of
bits/bytes or words it can store.
◼ The memory access time (read access and
write access): How long the memory takes
to load the data on to its data lines after it
has been addressed or how fast it can store
the data upon supplied through its data
lines.
Common Memory Types
 RAM: “Random-access” memory
• -Typically volatile memory
– bits are not held without power supply
• Read and written to easily during execution
• Internal structure more complex than ROM
– a word consists of several memory cells, each storing 1 bit
– each input and output data line connects to each cell in its
column
◼ – rd/wr signal lines connected to every cell

◼ – when row is enabled by decoder, each cell has logic that

stores input data bit when rd/wr indicates write or outputs

stored bit when rd/wr indicates read
 Basic types of RAM
SRAM: Static RAM
◼ Memory cell use flip-flops to store data
◼ Requires 6 transistors
◼ Holds data as long as power supplied
◼ Relatively insensitive to disturbances
such as electrical noise.
◼ Faster and more expensive than DRAM.
 DRAM - Dynamic RAM
◼ Dynamic RAM has cells whose charge leak despite
the availability of constant power supply and
hence need to be refreshed every 10-100 ms.
◼ Stores each bit of data in a separate capacitor
◼ the capacitor can be either charged or discharged
◼ Sensitive to disturbances
◼ Slower and cheaper than SRAM.
 Read Only Memory (ROM)
◼ This is a nonvolatile memory.
◼ It can only be read from but not written
to, by a processor in an embedded
system.
◼ Traditionally written to, “programmed”,
before inserting to embedded system.
ROM Uses
◼ Store software program for general-
purpose processor
◼ Program instructions can be one or
more ROM words
◼ Store constant data needed by system
◼ Implement combinational circuit
 Mask-programmed ROM
◼ The connections are “programmed” at
fabrication. It can be written only once (in
the factory). But it stores data for ever.
◼ Thus it has the highest storage
permanence. The bits never change
unless damaged.
◼ These are typically used for final design
of high-volume systems.
 OTP ROM: One-time
programmable ROM
◼ The Connections are “programmed” after manufacture by
user. The user provides file of desired contents of ROM.
The file input to machine called ROM programmer. Each
programmable connection is a fuse. The ROM
programmer blows fuses where connections should not
exist.
◼ Very low write ability: typically written only once and
requires ROM programmer device
◼ Very high storage permanence: bits don’t change unless
reconnected to programmer and more fuses blown
◼ Commonly used in final products: cheaper, harder to
inadvertently modify
 EPROM: Erasable
programmable ROM
◼ The programmable component is a MOS transistor. This
transistor has a “floating” gate surrounded by an
insulator. The Negative charges form a channel between
source and drain storing a logic 1. The Large positive
voltage at gate causes negative charges to move out of
channel and get trapped in floating gate storing a logic
0. The (Erase) Shining UV rays on surface of floating-
gate causes negative charges to return to channel from
floating gate restoring the logic 1. An EPROM package
showing quartz window through which UV light can
pass.
 The EPROM has

• Better write ability

– can be erased and reprogrammed
thousands of times
• Reduced storage permanence
– program lasts about 10 years but is
susceptible to radiation and electric noise
• Typically used during design development
EEPROM
◼ Electrically Erasable and Programmable
Read Only Memory.
◼ It is erased typically by using higher
than normal voltage. It can program
and erase individual words unlike the
EPROMs where exposure to the UV light
erases everything.
EEPROM has
◼ Better write ability
– can be in-system programmable with built-in circuit to provide
higher than normal voltage
• built-in memory controller commonly used to hide details
from memory user
– writes very slow due to erasing and programming
• “busy” pin indicates to processor EEPROM still writing
– can be erased and programmed tens of thousands of times
• Similar storage permanence to EPROM (about 10 years)
• Far more convenient than EPROMs, but more expensive
Flash Memory
◼ It is an extension of EEPROM. It has the same
floating gate principle and same write ability and
storage permanence. It can be erased at a faster rate
i.e. large blocks of memory erased at once, rather
than one word at a time.
◼ The blocks are typically several thousand bytes large
◼ Used with embedded systems storing large data
items in nonvolatile memory
◼ – e.g., digital cameras, TV set-top boxes, cell phones
 Memory Hierarchy
◼ The total memory capacity of a computer can be
visualized by hierarchy of components.
◼ The memory hierarchy system consists of all storage
devices contained in a computer system from the slow
Auxiliary Memory to fast Main Memory and to smaller
Cache memory.
◼ To bridge the processor memory performance gap,
hardware designers are increasingly relying on
memory at the top of the memory hierarchy to close
/ reduce the performance gap. This is done through
increasingly larger cache hierarchies (which can be
accessed by processors much faster), reducing the
dependency on main memory which is slower.
 An Example Memory Hierarchy
L0:
registers CPU registers hold words retrieved
from L1 cache.
Smaller,
faster, L1: on-chip L1
and cache (SRAM) L1 cache holds cache lines retrieved
from the L2 cache memory.
costlier off-chip L2
(per byte) L2:
cache (SRAM) L2 cache holds cache lines
storage retrieved from main memory.
devices
L3: main memory
Larger, (DRAM)
Main memory holds disk
slower, blocks retrieved from local
and disks.
cheaper local secondary storage
L4:
(per byte) (local disks)
storage Local disks hold files
retrieved from disks on
devices remote network servers.

L5: remote secondary storage

(distributed file systems, Web servers)
Chip/ IC/ microchip
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