COUNTERS

❑ Flip flops are essential components in clocked sequential circuits.

❑ Circuits that include flip flops are usually classified by the function they perform. Example – Registers,
Counters

❑ Purpose of counters – to count the number of occurrences of input

❑ Used to record the number of events occurring in a specified interval of time.

❑ Output increases by one in each clock cycle and comes back to 0 after reaching the maximum value.

❑ The combinations of flip-flops that perform counting function are known as Counters.

❑ Uses to record – no. of bits sent or received.

- no. of steps preformed in a computation
- Program counter increments once in each clock cycle and executes
the next instruction.
ASYNCHRONOUS COUNTERS
❑ N-bit counter will have N flip-flops and 2N states.

❑ Counters classification - Asynchronous/Ripple/Serial

- Synchronous/Parallel Counter

Asynchronous Counters

❑ Do not employ universal clock.

❑ Only the first flip-flop is driven by external clock signal.

❑ Clock input of the following flip-flops is driven by the output of the previous stage flip-flops.

❑ Flip-flops in the counter circuit do not change states simultaneously because they do not have a common
clock pulse.

❑ Simple, less hardware but have speed limitation.

SYNCHRONOUS COUNTERS
❑ Employ a universal clock.

❑ Clock signal is applied to all flip-flops in synchronization.

❑ Clock input of all the flip-flops is common, so output changes in parallel.

❑ Operate on higher speed/frequency in comparison to asynchronous counters because of lack of cumulative

delay of flip-flops.

❑ More hardware requirements.

UP/DOWN COUNTERS
❑ Both synchronous and asynchronous counters are also classified on the basis of direction in which the
counting progresses:

- Up counters 00 01 10 11 00

- Down counters 00 11 10 01 00

- Up/Down counters Works both ways

2-BIT SYNCHRONOUS BINARY COUNTERS
❑ JK flip-flops are preferred for synchronous counters.

❑ D and T flip-flops can also be used but they require for more circuitry due to absence of toggle and no change
states.

❑ Initial state – Both flip-flops are reset. State – Q1Q0 - 00

❑ 1st clock pulse – FFO – Toggle, Q0 - HIGH

- FF1 - No change, Q1 – LOW State – Q1 Q0 - 01
2-BIT SYNCHRONOUS BINARY COUNTERS
After Clock 1 – Q0 – HIGH, Q1 - LOW

❑ 2nd clock pulse – FFO – Toggle, Q0 - LOW

- FF1 - Toggle, Q1 – HIGH State – Q1Q0 – 10

❑ 3rd clock pulse – FFO – Toggle, Q0 - HIGH

- FF1 - No change, Q1 – HIGH State – Q1Q0 – 11

❑ 4th clock pulse – FFO – Toggle, Q0 - LOW

- FF1 - Toggle, Q1 – LOW State – Q1Q0 – 00
3-BIT SYNCHRONOUS BINARY COUNTERS
4-BIT SYNCHRONOUS BINARY COUNTERS
SYNCHRONOUS DECADE COUNTER

J0 = K0 = 1

J1 = K1 = Q1 Q’3

J2 = K2 = Q1 Q0

J3 = K3 = Q2 Q1 Q0 + Q3 Q0
SYNCHRONOUS DECADE COUNTER
❑ Initial state – Both flip-flops are reset. State – Q3 Q2 Q1Q0 - 0000

❑ 1st clock pulse – FFO – Toggle, Q0 - 1

- FF1 - No change, Q1 – 0
- FF2 – No change, Q2 – 0
- FF3 – No change, Q3 – 0 State – 0001

❑ 2nd clock pulse – FFO – Toggle, Q0 - 0

- FF1 - Toggle, Q1 – 1
- FF2 – No change, Q2 – 0
- FF3 – No change, Q3 – 0 State – 0010

❑ 3rd clock pulse – FFO – Toggle, Q0 - 1

- FF1 - No change, Q1 – 1
- FF2 – No change, Q2 – 0
- FF3 – No change, Q3 – 0 State – 0011
SYNCHRONOUS DECADE COUNTER
❑ 4th clock pulse – FFO – Toggle, Q0 - 0
- FF1 - Toggle, Q1 – 0
- FF2 – Toggle, Q2 – 1
- FF3 – No change, Q3 – 0 State – 0100

❑ 5th clock pulse – FFO – Toggle, Q0 - 1

- FF1 - No change, Q1 – 0
- FF2 – No change, Q2 – 1
- FF3 – No change, Q3 – 0 State – 0101

❑ 6th clock pulse – FFO – Toggle, Q0 - 0

- FF1 - Toggle, Q1 – 1
- FF2 – No change, Q2 – 1
- FF3 – No change, Q3 – 0 State – 0110

❑ 7th clock pulse – FFO – Toggle, Q0 - 1

- FF1 - No change, Q1 – 1
- FF2 – No change, Q2 – 1
- FF3 – No change, Q3 – 0 State – 0111
SYNCHRONOUS DECADE COUNTER
❑ 8th clock pulse – FFO – Toggle, Q0 - 0
- FF1 - Toggle, Q1 – 0
- FF2 – Toggle, Q2 – 0
- FF3 – Toggle, Q3 – 1 State – 1000

❑ 9th clock pulse – FFO – Toggle, Q0 - 1

- FF1 - No change, Q1 – 0
- FF2 – No change, Q2 – 0
- FF3 – No change, Q3 – 1 State – 1001

❑ 10th clock pulse – FFO – Toggle, Q0 - 0

- FF1 - No change, Q1 – 0
- FF2 – No change, Q2 – 0
- FF3 – Toggle, Q3 – 0 State – 0000
SYNCHRONOUS DECADE COUNTER
ASYNCHRONOUS COUNTERS
❑ Also called ‘Ripple Counters’

❑ No common CLOCK pulse

❑ Output of one flip-flop is connected to the CLOCK input of the next stage flip-flop.

❑ 2-bit asynchronous counter-

Q1Q0
Initial stage - 00
1st CLK - 01
2nd CLK - 10
3rd CLK - 11
4th CLK - 00
4-BIT ASYNCHRONOUS COUNTER

Q3 Q2 Q1 Q0

Initial stage - 0000 4th - 0100 8th - 1000 12th - 1100 16th - 0000

1st - 0001 5th - 0101 9th - 1001 13th - 1101

2nd - 0010 6th - 0110 10th - 1010 14th - 1110

3rd - 0011 7th - 0111 11th - 1011 15th - 1111

4-BIT ASYNCHRONOUS COUNTER
ASYNCHRONOUS DECADE COUNTER

0000 – 0001 – 0010 – 0011 – 0100 – 0101 – 0110 – 0111 – 1000 – 1001 – 0000
ASYNCHRONOUS DECADE COUNTER
❑ The counter counts upwards with clock signal starting from 0000 till 1001.

❑ After 1001, QA = QD = 1, AND gate output = 1

❑ All the flip-flops would be cleared implying that they would all be reset i.e. 0 state.
ASYNCHRONOUS COUNTER USING T FLIP-FLOP
ASYNCHRONOUS COUNTER USING D FLIP-FLOP
3-BIT SYNCHRONOUS UP-DOWN COUNTER

1 2 3
3-BIT SYNCHRONOUS UP-DOWN COUNTER
❑ Attributes of an up and down counter are combined in a single counter.

❑ If the output of every flip-flop (Q) within a counter is received on every next flip-flop, then it acts as an up-
counter.

❑ If the complemented output of every flip-flop present inside the counter is received on every next flip-flop,
such a counter is a down counter.

❑ The count up control line and count down control line decide the mode of operation of the counter.

J0 = K0 = 1

J1 = K1 = (A . COUNT-UP) + (A . COUNT-DOWN)

J2 = K2 = (B . COUNT-UP) + (B . COUNT-DOWN)
3-BIT SYNCHRONOUS UP-DOWN COUNTER

CLOCK

A
UP
B
C

A
CLOCK

DOWN B

C
4-BIT BINARY COUNTER WITH PARALLEL LOAD
❑ Counters employed in digital systems quite often require a parallel load capability for transferring an initial binary
number before the count operation.

❑ The binary counter has a parallel load capability and can also be cleared to 0.

❑ The input load control when equal to I disables the count operation and causes a transfer of data from the four
parallel inputs into the four flip-flops (provided that the clear input is 0).

❑ If the clear and load inputs are both 0 and the increment input is I, the circuit operates as a binary counter.
4-BIT BINARY COUNTER WITH PARALLEL LOAD
4-BIT BINARY COUNTER WITH PARALLEL LOAD
❑ Clear = 0, clears the counter, irrespective of its state.

❑ When Clear = 1, then only LOAD and COUNT operations take place.

❑ LOAD = 1, causes transfer of inputs into the register at the positive edge of the CLOCK pulse.

❑ COUNT = 1, causes the circuit to count to next binary state.

CLR CLK Load Count Function

0 X X X Clear to 0

1 1 X Load inputs

1 0 1 Count next binary state

1 0 1 No change
SYNCHRONOUS COUNTER DESIGN
❑ Procedure:

1. Obtain the state diagram – shows the progression of states through which counter advances.

2. List down the next state table.

3. List down the flip flop transition table.

4. Using K-maps, determine the simplified logic functions for the flip flops.

5. Draw the circuit.

MOD-4 SYNCHRONOUS UP COUNTER WITH JK FLIP FLOP
❑ Step 1 – State Transition Diagram

❑ Steps 2 and 3
MOD-4 SYNCHRONOUS UP COUNTER WITH JK FLIP FLOP
❑ Step 4
MOD-4 SYNCHRONOUS UP COUNTER WITH JK FLIP FLOP
❑ Step 5
EXAMPLE
❑ Design a synchronous counter using D flip flops that goes through states 0, 1, 2, 4, 0. The unused states must
always go to zero on the next clock pulse.
EXAMPLE

Present State Next State Required Excitation

Q3 Q2 Q1 Q3 Q2 Q1 D3 D2 D1

0 0 0 0 0 1 0 0 1

0 0 1 0 1 0 0 1 0

0 1 0 1 0 0 1 0 0

0 1 1 0 0 0 0 0 0

1 0 0 0 0 0 0 0 0

1 0 1 0 0 0 0 0 0

1 1 0 0 0 0 0 0 0

1 1 1 0 0 0 0 0 0

D1 = Q’3 Q’2 Q’1

D2 = Q’3 Q’2 Q1

D3 = Q’3 Q2 Q’1
EXAMPLE
3-BIT UP COUNTER (GRAY CODE) USING JK FLIP FLOPS
3-BIT UP COUNTER (GRAY CODE)
3-BIT UP COUNTER (GRAY CODE)
SHIFT REGISTER COUNTERS
❑ Shift registers with the serial output connected back to the serial input.

❑ They are classified as counters because they give a specified sequence of states.

❑ Two common types: the Johnson counter and the Ring counter.

RING COUNTER

❑ One flip-flop (stage) for each state in the sequence.

❑ The output of the last stage is connected to the D input of the first stage.

❑ An n-bit ring counter cycles through n states.

MOD-6 RING COUNTER

100000
Clock Q0 Q1 Q2 Q3 Q4 Q5
0 1 0 0 0 0 0 000001 010000
1 0 1 0 0 0 0
2 0 0 1 0 0 0 000010 001000
3 0 0 0 1 0 0
4 0 0 0 0 1 0 000100
5 0 0 0 0 0 1
RING COUNTER TIMING DIAGRAM
RING COUNTER
❑ Ring Counters can be implemented using D and JK flip flops.

❑ Only 4 of the 15 available states are utilized.

❑ Applications –

i) Used for counting data in a continuous loop

ii) Used as square-wave generators

iii) Used as oscillators

JOHNSON COUNTER (TWISTED RING COUNTER)
❑ The complement of the output of the last stage is connected back to the D input of the first stage.

❑ Require fewer flip-flops than ring counters but more flip-flops than binary counters.

❑ An n-bit Johnson counter cycles through 2n states.

MOD-8 JOHNSON COUNTER

MOD-8 JOHNSON COUNTER

❑ Used in LEDs

❑ To detect certain
patterns