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  • UVM Meeting 2 19-11-21

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    armando broncas
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    Simulation time is consumed by posedge clk and delays like #10ns, but not by UVM macros or interface connections. UVM testbenches have a hierarchy with an Environment class, Base test class, and specific test classes that instantiate a DUT module and interface.

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    UVM_meeting_2_19-11-21

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    Simulation time is consumed by posedge clk and delays like #10ns, but not by UVM macros or interface connections. UVM testbenches have a hierarchy with an Environment class, Base test class, and specific test classes that instantiate a DUT module and interface.

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    10 views2 pages

    UVM Meeting 2 19-11-21

    Uploaded by

    armando broncas
    Simulation time is consumed by posedge clk and delays like #10ns, but not by UVM macros or interface connections. UVM testbenches have a hierarchy with an Environment class, Base test class, and specific test classes that instantiate a DUT module and interface.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 2

    UVM – Time consumption in testbenches

    Time consumption refers to simulation time, not time to execute the testbench software
    instructions.
    uvm macros does not consume time.
    interface connections does not consume time.

    @(posedge clk) consumes time.


    #10ns, consumes time.
    UVM – UVM testbench
    Testbench and tests.
    Testbench (module)
    Specific test n
    Specific test 2
    Specific test 1
    Base test (class)

    Environment
    (class)
    DUT Interface
    Virtual IF
    (module)

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