Jalisco on Chip

Universal Verification Methodology course

References:
1) https://verificationacademy.com/verification-methodology-reference/uvm/do
cs_1.2/html/index.html
2) UVM 1.2 User’s Guide
3) https://verificationacademy.com/cookbook
UVM – Chapter 1 content

Chapter 1: Universal Verification Methodology Overview

Content:
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Pre-Si verification
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Evolution of verification methodologies
●
UVM characteristics
●
UVM phases
●
UVM testbench and tests
●
UVM configuration
 UVM – Pre-Si verification
Specification
Physical Testing/
Architecture RTL design Tape out
design Manufacture
Microarchitecture Volume
shipment
Verification Validation
 UVM – Pre-Si verification
Specification
Physical Testing/
Architecture RTL design Tape out
design Manufacture
Microarchitecture Volume
shipment
Verification Validation

●
50%-80% of development schedule ●
Main goal: correctness before TO
●
Simulation (functional verification) ●
Verification levels:
●
Formal verification – Block level
●
Emulation – IP level
●
Prototyping
– Sub-system level
– SoC level
UVM – Verification evolution
UVM – UVM basics
UVM stands for Universal Verification Methodology, which is a methodology built on
SystemVerilog language.

UVM focuses on:

●
Reducing verification coding effort
●
Enhancing code reuse
– Standard testbench structure
– Standard stimulus generation
UVM – UVM basics
UVM stands for Universal Verification Methodology, which is a methodology built on
SystemVerilog language.

UVM focuses on: Provides four service mechanisms:

●
Reducing verification coding effort ●
Reporter
●
Enhancing code reuse ●
Factory
– Standard testbench structure ●
Configuration database
– Standard stimulus generation ●
Simulation execution manager
UVM – UVM characteristics
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Open source methodology
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Utilizes TLM (Transaction-Level Modeling) communication to improve the
modularity and re-usability of testbench components.
●
UVM library is based in SystemVerilog
●
Separates the Test from the verification Environment (test customizes the
environment for a particular case)
●
The UVM-based testbench are executed in phases, thus, separating the creation of
components, from their connection and configuration.
UVM – UVM phases
UVM – UVM phases
pre_reset
reset
post_reset
pre_configure
configure
post_configure
Run run
phases pre_main
main
post_main
pre_shutdown
shutdown
post_shutdown
UVM – UVM phases
To start the execution of an UVM testbench, the run_test() method has to be called from
the static part of the testbench. It is usually called from within an initial block in the top
level module of the testbench.
Calling run_test() constructs the UVM environment root component and then initiates
the UVM phasing, performing the following process.

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Implementation of components
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Automatic and hierarchical threading
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Build phases – configure and construct components
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Run phase, consumes time, test cases
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Clean up phases – collect data into log and report