Professional Documents
Culture Documents
Architecture Specification
Design Specification
Synthesis
Physical Design
Timing analysis
Tape out
Verilog / SystemVerilog Event Scheduling
time slot
From previous
time slot Pre-poned sampling
process, continous
Active assignment, primitives
$monitor
$strobe
Post-poned To next
time slot
V Model
Acceptance
Requirements
Testing
System
Specification
Testing
Architecture Integration
Design Testing
Detailed
Unit testing
Design
Coding
W Model
Starting Test Acceptance Exec. , Debug.
Requirements
Activity Testing & Changing
Coding
Mediul de verificare
TOP
INTERFACE
Test Case
Environment
TOP
Clock Generator
DUT
Interface
Assertion
Test Case
Environment
Stimulus
Driver
Monitor
Reference Model
Scoreboard
Coverage
Mediul de verificare - OVM
Componentele mediului de verificare si interconectarea lor
Domeniul de Control
SCOREBOARD
TEST
CONTROLLER
COVERAGE
CHECKER CHECKER
MONITOR MONITOR
MASTER /
DRIVER DUT RESPONDER SLAVE
STIM.GEN
SCOREBOARD
TEST COVERAGE
CONTROLLER
AGENT CHECKER
(DE INTERFATA)
MONITOR
MASTER / PUT
PUT
DRIVER DUT
STIM.GEN
CHECKER AGENT
(DE INTERFATA)
MONITOR
Agent funcțional
SCOREBOARD
MONITOR MONITOR
DUT
Monitor BACKDOOR
SCOREBOARD
MONITOR
MONITOR MONITOR
BACK-DOOR
DUT