`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 29.10.2022 22:51:49
// Design Name:
// Module Name: Tx_32
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////

module uart_tx_32(
input clk,
input enable,
output tx_out,
output reg tx_done
);

wire [31:0]tx_data32 = 32'hABCDEF12;

wire tx_empty,txclk;
wire [7:0]tx_data;

reg [31:0]data;

assign tx_data = data[31:24]; //Change this to first 8 bit of MSB

reg load_send;
reg [2:0]state;
reg [2:0]count;

always @ (posedge txclk)begin

if(enable) begin
state <= 0;
data <= tx_data32;
load_send <= 1;
tx_done <= 0;
count <= 0;
end else begin
case(state)
3'd0:
begin
load_send <= 1;
state <= 1;
tx_done <= 0;
end
3'd1:
begin
 tx_done <= 0;
load_send <= 0;
if(tx_empty)
state <= 2;
else
state <= 1;
end
3'd2:
begin
count <= count +1;
load_send <= 1;
data <= (data << 8);
state <= 3;
tx_done <= 0;
end
3'd3:
begin
if(count == 4) //No of bytes
state <= 4;
else
state <= 0;
end
3'd4:
begin
tx_done <= 1;
load_send <= 1;
state <= 4;
end
default:
state <= 4;
endcase
end
end

//---------------------------- UART for 1 byte data transfer

----------------------------------------

assign ld_tx_data = load_send;

assign tx_enable = ~load_send;
uart_tx_clk clk0(clk,txclk);
uart_tx TX(enable,txclk,ld_tx_data,tx_data,tx_enable,tx_out,tx_empty);
//---------------------------------------------------------------------------------
---------
endmodule

module uart_tx_clk(
input clk,
output reg clk_out

);

reg [20:0]count;
always @ (posedge clk)begin
if(count == 868) //baud rate is 115200
count <= 0;
else
 count <= count + 1;

clk_out <= (count < 434)?1:0;

end
endmodule

module uart_tx(
reset ,
txclk ,
ld_tx_data ,
tx_data ,
tx_enable ,
tx_out ,
tx_empty
);

// Port declarations
input reset ; // to rst pin
input txclk ; // set Baud rate as txclk clock frequency
input ld_tx_data ; // load tx data to tx register when '1'
input [7:0] tx_data ; // tx data 8-bit data input
input tx_enable ; // transmit when enable
output tx_out ; // Serial port pin; goes to pin PACKAGE_PIN
C4(nexys4)
output tx_empty ; // give this pin to Spartan-3E LED
// Internal Variables
reg [7:0] tx_reg ;
reg tx_empty ;
reg tx_over_run ; //********************** Unused
reg [3:0] tx_cnt ; //counter
reg tx_out ; // serial output

// UART TX Logic
always @ (posedge txclk or posedge reset)
if (reset) begin
tx_reg <= 0;
tx_empty <= 1;
tx_over_run <= 0; //********************** Unused
tx_out <= 1; // default high
tx_cnt <= 0;
end else begin
if (ld_tx_data) begin//when 1
if (!tx_empty) begin // when 0(not empty)
tx_over_run <= 0;
end else begin
tx_reg <= tx_data;// load tx_data when empty
tx_empty <= 0;
end
end
if (tx_enable && !tx_empty) begin// when clk is high and reg is not empty and
tx_en is high

tx_cnt <= tx_cnt + 1;

if (tx_cnt == 0) begin
tx_out <= 0;//start bit
end
if (tx_cnt > 0 && tx_cnt < 9) begin//8 bit data
 tx_out <= tx_reg[tx_cnt -1];// shifting and transmitting
end
if (tx_cnt == 9) begin
tx_out <= 1;// stop bit 1
tx_cnt <= 0;
//done <= 1'b0;
tx_empty <= 1;// ready to take next data
end
end
if (!tx_enable) begin
tx_cnt <= 0;
end
end

endmodule

#############**************************XDC
FILE******************#######################
## This file is a general .xdc for the Nexys4 DDR Rev. C
## To use it in a project:
## - uncomment the lines corresponding to used pins
## - rename the used ports (in each line, after get_ports) according to the top
level signal names in the project

## Clock signal
set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk }];
#IO_L12P_T1_MRCC_35 Sch=clk100mhz
#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports
{CLK100MHZ}];

##Switches

set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports

{ enable }]; #IO_L24N_T3_RS0_15 Sch=sw[0]
#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports
{ reset }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]
set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports
{ ld_tx_data }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2]

## LEDs

set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports

{ tx_empty }]; #IO_L18P_T2_A24_15 Sch=led[0]
set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports
{ tx_done }]; #IO_L18P_T2_A24_15 Sch=led[0]
##USB-RS232 Interface

#set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports

{ UART_TXD_IN }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in
set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports
{ tx_out }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out
#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { UART_CTS
}]; #IO_L12N_T1_MRCC_35 Sch=uart_cts
#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { UART_RTS
}]; #IO_L5N_T0_AD13N_35 Sch=uart_rts