ICCAD Lecture 7, Nov.

2, 2007

High-Frequency Amplifier Design

£pª˜ŒìO¤ 1/35

1. Introduction
2. Zeros as Bandwidth Enhancers
3. The Shunt-Series Amplifier
4. Tuned Amplifiers
5. Neutralization and Unilateralization
6. Cascaded Amplifiers

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1. Ch. 9, “High-frequency amplifier design”, of Thomas Lee’s 2nd Ed.
Introduction
• The design of amplifiers at high frequencies demands more effort in
reaching the desired performance when approaching the inherent 2/35
limitations of the devices themselves.
• The effect of ever-present parasitic capacitances and inductances
can impose serious constraints on achievable performance.
• A collection of useful bandwidth extension techniques will be in-
troduced.
• It is possible to construct networks in which gain trades off more
with delay than with bandwidth.
 The Shunt-Peaked Amplifer
A standard common-source configuration with the addition of the
inductance, which provides the bandwidth enhancement.
3/35

• Qualitative analysis
– Frequency domain: introducing a ”zero”
– Time domain: step response
• Quantitative analysis: The impedance of the RLC network is
1 R[s(L/R) + 1]
Z(s) = (sL + R) k = 2 (1)
sC s LC + sRC + 1
 There are one zero and two poles in the transfer function of vOUT/iIN,
which is the impedance. The gain is gmZ(s).
s
(ωL/R)2 + 1
|Z(jω)| = R (2) 4/35
(1 − ω 2LC)2 + (ωRC)2
Note that
– Numerator, (ωL/R)2 % as ω %.
– Denomenator, (1 − ω 2LC)2 & as ω %.

Design task and procedure: Given R and C, determine L.

Introducing m = RC/(L/R) = RC/τ where τ = L/R. The
transfer function is then
R(τ s + 1)
Z(s) = 2 2 (3)
s τ m + sτ m + 1
or s
|Z(jω)| (ωτ )2 + 1
= (4)
R (1 − ω 2τ 2m)2 + (ωτ m)2
Define ω1 = 1/RC, the uncompensated -3-dB frequency,
v s
u  2
ω2 t u m2 m2
= − +m+1 + − + m + 1 + m2 (5)
ω1 2 2 5/35

The task is to choose m such that some desired behavior happens.

• To maximize the bandwidth. Setting dω2/dm = 0 leads to
√
m = 2 ≈ 1.41 (6)
and
ω2,max = 1.85ω1 (7)
Unfortunately, this m leads to a 20% peak in the frequency re-
sponse, which is undesirably high.
• To let |Z(jω1)| = R
√
q
m = 2 =⇒ ω = ω1 1+ 5 ≈ 1.8ω1 (8)
The peaking is substantially reduced, to about 3%.
• But there are cases where flat frequency response (no peaking)
is desired. Mathematical procedure: form an expression for the
frequency response magnitude (e.g., the square of the magnitude),
and maximize the number of derivatives whose value is zero at
ω = 0 (DC). 6/35

√
m = 1 + 2 ≈ 2.41 =⇒ ω−3−dB = 1.72ω1 (9)

• Some desired specification on the time response: “well behaved”,

meaning both flat frequency response and the preservation of phase
relationship among signal’s Fourier components. Observations:
– All frequencies delayed by an equal amount of time
– Phase shift is linearly proportional to the frequency
– Target is to minimize the deviation from this linearity.
dφ
TD (ω) ≡ − (10)
dω
– To provide an approx. to a constant delay over some finite
bandwidth, which can be realized by maximizing the number
of derivatives of TD (ω) whose value is zero at DC. The solution
to the following cubic eq. for m
m3 − 3m2 − 1 = 0 (11)
7/35
The relevant root is
s √ s √
3 3+ 5 3 3− 5
m=1+ + ≈ 3.10 (12)
2 2
which leads to ωTD = 1.6ω1.
 • Conditions for maximally flat frequency response and maximally
flat time delay do not coincide.
• Larger L (smaller m) gives a larger bandwidth extension but poorer
pulse fidelity.
8/35
• Smaller L yields less bandwidth improvement but better pulse re-
sponse.
Example: Design a 1.5 GHz CS broadband amplifier using m = 3.1,
given C = 1.5 pF and R = 100 Ω (f1 = 1.06 < 1.5 GHz).
Solution: L = R2C/m = 4.8 nH, leading to f2 = 1.7 GHz and
Q = 0.5 for the drain network. So onchip spiral inductors with modest
Q suffice.
Zeros as Bandwidth Enhancers

9/35

Pole-zero doublet:
ατ s + 1
H(s) = (13)
τs + 1
 Two-Port Bandwidth Enhancement
Employing a two-port network between the amplifier and load (shunt
peaking uses one-port network).
10/35

Figure 1: Shunt and series peaking; Shunt and double-series peaking

• Shunt-series peaking: additionally separating the load capacitance

from the output capacitance of the device.
Series peaking only (without L1):
√
– Maximum ω2 = 2ω1, smaller than shunt peaking (1.85).
 – Peaking is provided by complex poles.
– m ≡ R2C/L2 = 2: maximum bandwidth and maximally flat
amplitude
– m = 3: maximally flat group delay, ω2 = 1.36ω1.
11/35
• Double-series peaking
– Charges capacitances serially in time
– Trade-off delay for improved bandwidth
– To save die area, the combination of three inductors can be
realized by coupled inductors (transformer)
 R2CL CL 1 − k
L= Cc = (14)
2(1 + k) 4 1+k
• k = 1/3: maximally flat amplitude
• k = 1/2: maximally flat group delay 12/35

The theoretical
√ bandwidth improvement factor provided by this cir-
cuit is ω2 = 2 2ω1 = 2.83ω1, substantially better than the 1.7-GHz
bandwidth of the shunt-peaked case.
 The Shunt-Series Amplifier
An alternative approach to the design of broadband amplifiers is
to use negative feedback. The shunt-series amplifier has a relative
13/35
constancy of input and output impedances over a broad frequency
range, which makes cascading much less complicated. The design task

is to find R1 and RF given desired input-output resistances,Rin (and

Rout), and gain, Av .
• Effective gain, gm,eff or Gm:

14/35

id gm
Gm = =
vin 1 + gmR1
1
≈ if R1  1/gm (15)
R1
• Assume RF large enough (hence the loading on the output node
may be neglected), the voltage gain, Av = −RL/R1.
• RF reduces both input and output resistance through the shunt
feedback it provides.
 15/35

Figure 2: (a) Input test; (b) Output test

• To compute input resistance, Rin. Citing Miller effect

RF RF
Rin = ≈ (16)
1 − Av 1 + RL/R1

• To compute output resistance, Rout.

RF + RS RF
Rout = ≈ (17)
1 + RS /R1 1 + RS /R1
If RL = RS = R, then
RF RF
Rin ≈ Rout ≈ ≈ (18)
1 + R/R1 1 − AV
16/35
Gain and Input-Output Impedance of Shunt-Series
Amplifiers
Gate-to-drain gain:
• Applying a test voltage from gate to ground and using superposi- 17/35
tion,
RF RL RL
vout = −gm,eff vtest + vtest (19)
RF + RL RF + RL
   
vout RL 1 1 1
Av = =− · · · 1−
vtest R1 1 + 1/gmR1 1 + RL/RF gm,eff RF
(20)
A compact form
 
RL RF − RE
Av = − (21)
RE RF + RL
where RE = 1/gm,eff . The implication is that in order to obtain
the desired gain, one must choose a value of R1 (or RE ) that is
somewhat smaller than anticipated on the basis of the first-order
equations.
Input resistance:
RF RE (RF + RL)
Rin = = (22)
1 − AV RE + RL
18/35
• In general, one designs for a particular value of gain.
• The value of feedback resistance necessary to produce a desired
input resistance is readily found.
Output resistance:
RE (RF + RS )
Rout = (23)
RE + RS
• Qualitative analysis
– Low-order system: G · BW = const(ωT )
– Open-circuit time-constant (Oτ ’s) estimate of bandwidth is rea-
sonably accurate.
– Input impedance possesses a capacitive component
– Output impedance rises with frequency (inductive)
• Open-circuit time-constant analysis
– Effective resistance facing Cgd: RF in parallel with
RF k (RS + RL + gm,eff RS RL) (24)
19/35
In the limit of large gain, it approaches
R
|AV | (R = RS = RL) (25)
2
– Effective resistance facing Cgs (computation more involved) In
the limit of large gain,
R 1
(26)
R1 gm
– Observation: both open-circuit resistances are roughly propor-
tional to gain, the gain-bandwidth product of the shunt-series
amplifier is approximately constant.
  −1
Cgs RCgd
BW ≈ |AV | + (27)
gm 2
• Input impedance (capacitive component due to Cgs and Miller-
multiplied Cgd): assuming BW is controlled by a simple RinCin
constant.
1 |AV |
RinCin ≈ (BW)−1 =⇒ Cin ≈ Cgs + Cgd (28) 20/35
gmR1 2
The Miller-augmented Cgd dominates.
– The presence of this capacitance makes it impossible to achieve
a perfect input impedance match at all frequencies.
– Solutions: use L-match (inductance in series with the gate) to
transform at some nominal frequency
• Output Impedance: In the limit of high gain, it includes an induc-
tive component whose value is (neglect Cgd)
A2V RCgs
Lout ≈ (29)
gm
Explanation:
– Gate voltage (due to the applied test voltage on the drain) is
an attenuated and low-pass-filtered version of the applied drain
voltage: gate voltage lags behind the drain voltage.
– Drain current lags drain voltage (characteristic of indutance)
21/35
– But Cgd supplies a leading component of voltage at the gate
(capacitive and partially compensates the inductive nature).
Tuned Amplifier
• CS amplifier with single tuned load

22/35

– Driving from a zero-impedance source

– Neglect the series gate resistance
– Then, Cgd can be absorbed into C.
The circuit is thus an ideal transconductor driving an RLC tank.
– At the resonant freq., the gain is gmR.
– The total -3-dB bandwidth is 1/RC.
 – The product of gain (measured at resonance) and bandwidth is
1 gm
G · BW = gmR · = (30)
RC C
which is independent of the center freq. 23/35

The key is the cancellation of the load capacitance by the in-

ductor in the tuned amplifier.
• Detailed analysis
More realistic model: with RS (and rg )

– Admittance seen to the left of RLC tank (yout)

 The result is a parallel ReqCeq with
Req = RS + rg (31)
Ceq = Cgd[1 + gmReq] = Cgd[1 + gm(RS + rg )] (32)
24/35
This is the alternative manifestation of the Miller effect viewed
from the output port. The components in the responsive cur-
rent:
∗ Resistive (due to capacitive voltage divider)
∗ Capacitive (due to RS + rg )
– Admittance seen to the right of Cgs: using the superposition
principle:
yL yF gmyF
yin = + (33)
yL + yF yL + yF
where yF = jωCgd and yL is the admittance of the RLC tank.
Often, |yF |  |yL|, then
gm(jωCgd)
yin ≈ yF + (34)
yL
Observations
∗ yL has a net negative imaginary part at freq.s where the tank
looks inductive (i.e., below resonance)
∗ 2nd term on RHS of the above eq. can have a negative real
part.
25/35
∗ Input of the circuit can act as if a negative resistor were
connected to it.
∗ All are caused by the presence of Cgd, which may be as much
as 30-50% of the main gate capacitance.
Neutralization and Unilateralization
Neutralization: Cannot be done precisely for Cgd is voltage-dependent.

26/35
 Unilateralization and Source-coupled version of cascode amplifier:
trade-off: for given total current and headroom

27/35
Cascaded Amplifiers
• Questions to answer:
– How many amplifier stages to use to achieve a certain gain?
28/35
– Given a BW for each stage, what is the BW of the overall
amplifier?
– Any optimum number of stages to maximize the overall BW?
• Bandwidth shrinkage
Assumption: each stage has a unit DC gain and a single pole
1
H(s) = (35)
τs + 1
A cascade of n such amplifiers
 n
1
A(s) = (36)
τs + 1
 1 n
 
|A(jω)| =   = √1 (37)
jωτ + 1  2
so that !n
1 1
p =√ (38)
(ωτ )2 +1 2
The bandwidth is 29/35
1 p 1/n
ω= 2 −1 (39)
τ
As n approaches infinity, the overall bandwidth tends toward zero.
To make the physics more clear,
 
1
21/n = exp[ln(21/n)] = exp ln 2 (40)
n
For large n,  
1 1
exp ln 2 ≈ 1 + ln 2 (41)
n n
Thus r
1p 1 1 0.833
ω= 21/n − 1 ≈ ln 2 ≈ √ (42)
τ τ n τ n
 The error for n = 1 is 17%, and 2 8%, 3 6%, drops pretty fast as n
increases. The open-circuit, time-constant method would predict
the bandwidth goes directly as 1/n, while in fact it goes as the
reciprocal square root.
30/35
• Optimum gain per stage
Assuming each stage is identical and with constant gain-bandwidth
product. The goal is to find the number of stages that, for a given
overall gain requirement, maximizing the bandwidth (hence the
overall gain-bandwidth product).
– Overall gain, G, meaning Gss = G1/n
– Gain-bandwidth product for each stage: ωT
ωT
BWss = 1/n (43)
G
The bandwidth for the total amplifier:
√
ωT ln 2
BWtot ≈ 1/n √ (44)
G n
or
1 1 √ 1/n

≈ √ nG (45)
BWtot ωT ln 2
The maximum total bandwidth is achieved when
31/35
d √ 1/n

nG =0 (46)
dn
which yields
1
ln(G1/n) = =⇒ G1/n = e1/2 = 1.649 (47)
2
The number of stages corresponding to this optimum is
n = 2 ln G (48)
The overall bandwidth in this case is
r
ln 2 0.357
BWtot = ωT ≈√ ωT (49)
2e ln G ln G
It can be seen when n is chosen optimally (knowing G), the product
of the bandwidth and the square root of the log of the gain is a
constant. The overall bandwidth is relatively insensitive to the
value of overall gain.
Conclusion: a constant gain-bandwidth product is only a property
of single-pole systems. This relationship breaks down when the
32/35
order of the system grows to large values.
Distributed Amplifier
Achieving a gain-for-delay tradeoff without affecting bandwidth

33/35

• A voltage step applied to the input

• The input propagates down the input line, causing a step to appear
at each transistor in succession.
• Each transistor generates a current (gmVstep)
• Ultimately all the transistor output currents are summed in time
coherence
Overall gain:
ngmZ0
AV = (50)
2
This amplifier has an overall gain that depends linearly on the number
of stages. Thus each stage can operate at frequencies where the gain 34/35

is smaller than unity.

• Can operate at substantially higher frequencies than conventional
amplifiers
• Since delay is proportional to the number of stages, it trades gain
for delay, not bandwidth.
• Transistor input/output capacitances are absorbed by delay line.
• Each stage can have a gain smaller than unity, hence higher BW.
• Power hungry
History and current status:
• Invented in 1936 in U.K. by Percival, landmark paper by Hewlett,
et al. in 1948.
• Vacuum tube implementation in Tektronix oscilloscope (100MHz) 35/35

in 1960.
• Reappeared in 1980 in GaAs technology. Compound semiconduc-
tor realization: InP version of 100-GHz BW.
• CMOS distributed amplifier: 25 GHz using 0.18 µm technology
(1999)