PHN-314 Microprocessors & Peripheral Devices (Spring 2023)

Assignment 1

1. Problem 5, Ch. 3 of Ref. [1].

2. Problem 16, Ch. 3 of Ref. [1].

3. Problem 22, Ch. 3 of Ref. [1].

4. Problem 24, Ch. 3 of Ref. [1].

5. Problem 30, Ch. 3 of Ref. [1].

6. Problem 37 Ch. 3 of Ref. [1].

7. (a) Find the address range of 6116 RAM shown in Fig. 1. Refer to Fig. 3.23 of
Ref. [1] for the pin diagram of 74LS138.
(b) Design an interfacing scheme yielding highest possible address range for the
memory shown in Fig. 1.

Figure 1: Interfacing RAM 6116.

8. Explain the meaning of ”Random Access” in the acronym RAM.

9. (a) What is the maximum memory size M addressable by 8 address lines?

(b) Draw a coincident address decoding scheme for an M x8 memory using two 4-
to-16 line decoders.
10. Fig. 2 shows internal logic of a 32x8 ROM with address lines A0-A4 and data lines
D0-D7. Draw the internal logic after programming it according to the following
truth-table.

Address Data (Hex)

00000 3E
00001 FF
00010 D3
00011 40
00100 EF
00101-11111 00

Figure 2: A programmable 32x8 ROM (adapted from [2]).

11. List all externally-initiated input pins of the microprocessor 8085 and explain their
usage.

12. Problem 3, Ch. 4 of Ref. [1].

13. Problem 6, Ch. 4 of Ref. [1].

14. Problem 8, Ch. 4 of Ref. [1].

15. Problem 10, Ch. 4 of Ref. [1].

16. Problem 13, Ch. 4 of Ref. [1].

17. Problem 16, Ch. 4 of Ref. [1].

18. Consider an interfacing logic for LED output port interfaced with an 8085 micro-
processor (with de-multiplexed AD0-AD7 lines) shown in Fig. 4.
(a) What is the address of the latch?
(b) Write an instruction to output the content of the accumulator to the LED port.
(c) Draw a timing diagram showing signals IO/M, WR, IOADR and IOSEL for
the last three clock cycles of the instruction in the part (b).

Figure 3: Interfacing LED output port (reproduced from [1]).

19. With help of a timing diagram, show that the following circuit generates one wait
state. Here, both D flip-flops are rising edge-triggered and the CLEAR pin is active-
low.

Figure 4: A wait-state generation circuit (reproduced from [3]).

20. Draw a timing diagram for the following instruction, showing status lines IO/M,
S1, S0, ALE; address/data lines AD0-AD7, A8-A15; and control lines RD, WR.
Mention the addresses and data at appropriate places.
Address Opcode Mnemonics
2000 3E 80 MVI A, 80
21. Draw the state transition sequence for the following program assuming no HOLD,
RESET or valid interrupt occurs.
MOV A, C
ADD B
HLT
22. Problem 3, Ch. 6 of Ref. [1].
23. Problem 8, Ch. 6 of Ref. [1].
24. Problem 13, Ch. 6 of Ref. [1].
25. Problem 28, Ch. 6 of Ref. [1].
26. Problem 30, Ch. 6 of Ref. [1].
27. Problem 35, Ch. 6 of Ref. [1].
28. Problem 18, Ch. 7 of Ref. [1].
29. Problem 29, Ch. 7 of Ref. [1].
30. (a) Describe a procedure for multiplying two (unsigned) binary numbers with help
of a suitable example.
(b) Write an 8085 assembly language program to multiply two binary numbers
stored at locations 2050H and 2051H, and store the result in HL register pair.
(c) Assuming a 3 MHz internal clock, calculate the time required for execution of
the code for the numbers used in the part (a).

References
1. R. Gaonkar, ”Microprocessor architecture, programming and applications”, Sixth
Edition, Penram Publications.
2. M. M. Mano and M. D. Ciletti, ”Digital design”, Fifth Edition, Pearson India.
3. MCS 80/85 Users Manual, Intel Corporation.