Preliminary

Arora V series of FPGA Products

Package & Pinout User Guide

UG983-1.0E, 01/05/2023
 Preliminary

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 Preliminary

Revision History
Date Version Description
01/05/2023 1.0E Initial version published.
 Preliminary Contents

Contents

Contents ................................................................................................................. i
List of Figures ..................................................................................................... ii
List of Tables ...................................................................................................... iii
1 About This Guide .......................................................................................... 1
1.1 Purpose .............................................................................................................................. 1
1.2 Related Documents ............................................................................................................ 1
1.3 Terminology and Abbreviations ........................................................................................... 1
1.4 Support and Feedback ....................................................................................................... 1

2 Overview ........................................................................................................ 2
2.1 PB-Free Package ............................................................................................................... 2
2.2 Package and Max. User I/O Information ............................................................................ 2
2.3 Power Pins.......................................................................................................................... 3
2.4 Pin Quantity ........................................................................................................................ 3
2.4.1 Quantity of GW5AT-138 Pins ........................................................................................... 3
2.5 Pin Definitions ..................................................................................................................... 5
2.6 I/O BANK Introduction ........................................................................................................ 8

3 View of Pin Distribution ................................................................................ 9

3.1 View of GW5AT-138 Pins Distribution ................................................................................ 9
3.1.1 View of FPG676A Pins Distribution ................................................................................. 9

4 Package Diagram ........................................................................................ 11

4.1 FPG676A Package Outline (27mm x 27mm) ....................................................................11

UG983-1.0E i
 Preliminary List of Figures

List of Figures

Figure 3-1 View of GW5AT-138 FPG676A Pins Distribution (Top View) ........................................... 9
Figure 4-1 Package Outline FPG676A .............................................................................................. 11

UG983-1.0E ii
 Preliminary List of Tables

List of Tables

Table 1-1 Terminology and Abbreviations .......................................................................................... 1

Table 2-1 Package, Max. User I/O Information, and LVDS Pairs ...................................................... 2
Table 2-2 Arora V Power Pins ............................................................................................................ 3
Table 2-3 Quantity of GW5AT-138 Pins ............................................................................................. 3
Table 2-4 Arora V series of FPGA Products Pin Definition ................................................................ 5
Table 3-1 Other pins in GW5AT-138 FPG676A ................................................................................. 10

UG983-1.0E iii
1 About This Guide Preliminary 1.1 Purpose

1 About This Guide

1.1 Purpose
This manual introduces Gowin Arora V series of FPGA products
package and provides pin definitions, a list of pin numbers, pin distribution
view, and package diagrams.

1.2 Related Documents

The latest user guides are available on the GOWINSEMI Website.
You can find the related documents at www.gowinsemi.com:
1. DS981, Arora V series of FPGA Products Data Sheet
2. UG982, GW5AT-138 Pinout

1.3 Terminology and Abbreviations

The terminology and abbreviations used in this manual are as shown
in Table 1-1.
Table 1-1 Terminology and Abbreviations
Terminology and Abbreviations Meaning
FPGA Field Programmable Gate Array
GPIO Gowin Programmable Input/Output
FPG FCPBGA Package

1.4 Support and Feedback

Gowin Semiconductor provides customers with comprehensive
technical support. If you have any questions, comments, or suggestions,
please feel free to contact us directly by the following ways.
Website: www.gowinsemi.com
E-mail: support@gowinsemi.com

UG983-1.0E 1(11)
2 Overview Preliminary 2.1 PB-Free Package

2 Overview

Gowin Arora V series of FPGA products are the five-generation of

Arora family with abundant internal resources, a new-architecture and
high-performance DSP supporting AI operations, high-speed LVDS
interfaces, and abundant BSRAM resources. At the same time, Arora V
series integrate self-developed DDR3, 12.5Gbps SERDES supporting
multiple protocols, and provide a variety of packages. They are suitable for
applications such as low power, high performance and compatibility
design.
Gowin provides a new generation of FPGA hardware development
environment that supports FPGA synthesis, placement & routing,
bitstream generation and download, etc.

2.1 PB-Free Package

Arora V series of FPGA products are PB free in line with the EU
RoHS environmental directives. The substances used in the Arora V
series of FPGA products are in full compliance with the IPC-1752
standards.

2.2 Package and Max. User I/O Information

Table 2-1 Package, Max. User I/O Information, and LVDS Pairs
Pitch Size E-pad Size
Package GW5AT-138 GW5A-138 GW5AT-60 GW5A-25
(mm) (mm) (mm)
FPG676A 1.0 27 x 27 - 312（150） - - -
Note!
For package type abbreviations employed in this manual, see 1.3 Terminology and
Abbreviations.

UG983-1.0E 2(11)
2 Overview Preliminary 2.3 Power Pins

2.3 Power Pins

Table 2-2 Arora V Power Pins
VCC VCCO0 VCCO1 VCCO2
VCCO3 VCCO4 VCCO5 VCCO6
VCCO7 VCCO10 VCCX VSS
VCCC VCC_REG Q0_VDDHA Q1_VDDHA
Q0_VDDT_IN0 Q0_VDDT_IN1 Q0_VDDT_IN2 Q0_VDDT_IN3
Q1_VDDT_IN0 Q1_VDDT_IN1 Q1_VDDT_IN2 Q1_VDDT_IN3
Q0_VDDD_IN0 Q0_VDDD_IN1 Q0_VDDD_IN2 Q0_VDDD_IN3
Q0_VDDTC_IN0 Q0_VDDTC_IN1 Q0_VDDTC_IN2 Q0_VDDTC_IN3
Q1_VDDD_IN0 Q1_VDDD_IN1 Q1_VDDD_IN2 Q1_VDDD_IN3
Q1_VDDTC_IN0 Q1_VDDTC_IN1 Q1_VDDTC_IN2 Q1_VDDTC_IN3
Q0_VDDA Q0_VDDTC Q1_VDDA Q1_VDDTC
M0_VDDA M0_VDDD M1_VDDA M1_VDDD
M0_VDDX M1_VDDX – –

2.4 Pin Quantity

2.4.1 Quantity of GW5AT-138 Pins
Table 2-3 Quantity of GW5AT-138 Pins
GW5AT-138
Pin Type
FPG676A
BANK0 (Q0) 0/0/0
BANK1 (Q1) 0/0/0
BANK2 50/24/24
BANK3 50/24/24
Single-ended IO/
BANK4 50/24/24
Differential pair/LVDS[1]
BANK5 50/24/24
BANK6 50/24/24
BANK7 50/24/24
BANK10 12/6/6
Max. User I/O 312
Differential Pair 150
True LVDS output 150
VCC 0
VCCX 0
VCCO0 0
VCCO1 0
VCCO2 6
VCCO3 6

UG983-1.0E 3(11)
2 Overview Preliminary 2.4 Pin Quantity

GW5AT-138
Pin Type
FPG676A
VCCO4 6
VCCO5 6
VCCO6 6
VCCO7 6
VCCO10 2
VCCX 3
VCC/VCCC 13
VCC_REG 6
Q1_VDDHA 1
Q0_VDDHA 1
Q1_VDDA/Q1_VDDD_IN0/Q1_VDDD_IN1/Q1_VDDD_I
N2/Q1_VDDD_IN3/Q1_VDDTC/Q1_VDDTC_IN0/Q1_V 3
DDTC_IN1/Q1_VDDTC_IN2/Q1_VDDTC_IN3
Q0_VDDA/Q0_VDDD_IN0/Q0_VDDD_IN1/Q0_VDDD_I
N2/Q0_VDDD_IN3/Q0_VDDTC/Q0_VDDTC_IN0/Q0_V 3
DDTC_IN1/Q0_VDDTC_IN2/Q0_VDDTC_IN3
Q1_VDDT_IN0/Q1_VDDT_IN1/Q1_VDDT_IN2/Q1_VD
2
DT_IN3
Q0_VDDT_IN0/Q0_VDDT_IN1/Q0_VDDT_IN2/Q0_VD
2
DT_IN3
M0_VDDA/M0_VDDD/M1_VDDA/M1_VDDD 4
M0_VDDX/M1_VDDX 1
VSS 120
MODE0 1
MODE1 1
MODE2 1
NC 102
Note!
Single-ended/Differential I/O quantity includes CLK pins and download pins.

UG983-1.0E 4(11)
2 Overview Preliminary 2.5 Pin Definitions

2.5 Pin Definitions

Arora V series of FPGA products have different pin locations in
different packages.
Table 2-4 provides a detailed overview of user I/O, multi-function pins,
dedicated pins, and other pins.
Table 2-4 Arora V series of FPGA Products Pin Definition
Pin Name I/O Description
User I/O
[End] indicates the pin location, including L(left), R(right),
B(bottom), T(top).
[Row/Column Number] indicates the pin Row/Column number.
If [End] is T(top) or B(bottom), [Row/Column Number] indicates
IO[End][Row/Column the column number of the corresponding CFU. If [End] is L(left)
I/O/LVDS or R(right), [Row/Column Number] indicates the row number of
Number][A/B]
the corresponding CFU.
[A/B] indicates differential signal pair information.
LVDS in the I/O column indicates that the pin supports LVDS
output only.
Multi-Function Pins
/MMM represents one or more of the other functions in
IO[End][Row/Column
addition to being general purpose user I/O. When these
Number][A/B]/MMM
functions are not in use, these pins can be used as user I/O.
D00 I/O CPU Mode: Data input/output (bidirectional) pin D00.
CPU Mode: Data input/output (bidirectional) pin D01
MSPI Mode: Serial data input in X1 mode; In X2 and X4
D01 I/O
modes, the input pin of parallel data bit 1 connected to pin
DQ1/Q/SO/IO1 of external Flash device
CPU Mode: Data input/output (bidirectional) pin D02
MSPI Mode: In X4 mode, the input pin of parallel data bit 2
D02 I/O
connected to pin DQ2/W#/WP#/IO2 of external Flash device
respectively
CPU Mode: Data input/output (bidirectional) pin D03
MSPI Mode: In X4 mode, the input pin of parallel data bit 3
D03 I/O
connected to pin DQ3/HOLD#/IO3 of external Flash device
respectively
D04~D07 I/O CPU Mode: Data input/output port D04~D07
D08~D31 I CPU Mode: Data input port D08~D31
ADCINCK0 I/O ADC0 dedicated clock input pin
ADCINCK1 I/O ADC1 dedicated clock input pin
Configuration Clock
Slave Mode: CCLK is input and needs to be connected to
CCLK I/O
external clock source
Master Mode: CCLK is output
Configuration Bank Voltage Selection Signal (1 for 3.3/2.5V)
Configuration Bank includes bank3, bank4, and bank10
CFGBVS I/O
The function of pin CFGBVS is 1; The default bank voltage is
3.3/2.5V

UG983-1.0E 5(11)
2 Overview Preliminary 2.5 Pin Definitions

Pin Name I/O Description

CFGPU I/O Weak pull-up selection signal pin during configuration
External Input Clock Signal
Master Mode: EMCCLK is used as the clock source of FPGA
EMCCLK I
configuration logic and output CCLK
Slave Mode: EMCCLK is not associated with slave mode
MCKTEST I/O MCLK CIB output test pin
FBTEST_L0 I/O Internal test pin
FBTEST_R0 I/O Internal test pin
CLKTEST_L0 I/O Internal test pin
CLKTEST_R0 I/O Internal test pin
MSPI Mode: Serial instruction and address output, in X2 and
MOSI I/O X4 modes, the output pin of parallel data bit 0 connected to pin
DQ0/D/SI/IO0 of external Flash device
CPU Mode: Chip select signal, active-low
Master CPU Mode: this pin can be connected to the chip
select signal of external configuration controller, or can be
grounded directly or grounded via a 1KΩ resistor Slave CPU
CSI_B I Mode: External configuration controller can select FPGA by
controlling CSI_B signal
In Master mode and Slave mode, the CSI_B signal is sent by
the external controller. Other modes are not associated with
CSI_B signal
Used to connect to the next-level device in FPGA cascade
configuration mode (Daisy Chain)
Serial Mode: Output the configuration data of the next-level
device
DOUT_CSO_B O
Master SPI Mode: Output the configuration data of the next-
level device
CPU Mode: Output the chip select signal of the next-level
device
Active-low. Weak pull-up selection signal pin during
configuration：
Enable internal weak pull-up resistor during configuration after
PUDC_B I FPGA power up
PUDC_B low: all GPIOs except PUDC_B weak pull-up
PUDC_B high: all GPIOs in high impedance
PUDC_B are not allowed to be left floating during configuration
CPU Mode: Data write/read controlling signal
When RDWR is high, FPGA outputs data, while RDWR is low,
external controller writes data into FPGA
Master CPU Mode: can be connected to external controller
RDWR signal; can be grounded directly or via a resistor ≤ 1KΩ
RDWR I
Slave CPU Mode: External controller RDWR signal
Low 8-bit dedicated IOs of CPU Mode will be affected by
RDWR status after wakeup; Low 8-bit dedicated IOs of CPU
Mode multiplexed as regular IOs will not be affected by
RDWR.
SSPI_CLK I/O SSPI/QSSPI configuration mode：clock input pin
SSPI_WPN I/O QSSPI Configuration Mode: Data input pin
SGCLKC_[x] I Differential input pin of SGCLKT_[x]. C(Comp). [x]: clock No.

UG983-1.0E 6(11)
2 Overview Preliminary 2.5 Pin Definitions

Pin Name I/O Description

Dedicated clock input pin driving the same clock domain.
SGCLKT_[x] I
T(True). [x]: clock No.
MGCLKC_[x] I Differential input pin of MGCLKT_[x], C(Comp), [x]: clock No.
Dedicated clock input pin driving multiple clock domains.
MGCLKT_[x] I
T(True). [x]: clock No.
VREF – Reference Voltage
DOUT O SERIAL Mode: Data output
I, internal
DIN weak pull- SERIAL Mode: Data input
down
I, internal
TMS weak pull- JTAG Mode: Serial mode input
up
TCK I JTAG Mode: Serial clock input
TDO O JTAG Mode: Serial data output
I, internal
TDI weak pull- JTAG mode: Serial data input
up
RECONFIG_N I Global Reset GowinCONFIG signal, active low
High, indicates the successful completion of programming and
configuration
O
Low, indicates the incompletion or failure of programming and
DONE[1] configuration
When the DONE signal is low, delay the start of the chip until
I
the DONE signal is high
High, indicates the device can be programmed and configured
currently
READY[1] O
Low, indicates the device cannot be programmed and
configured currently
MCS_N O MSPI Mode: Enable signal MCS_N, active low
SSPI Mode: Enable signal SSPI_CS_N, active low, and
SSPI_CS_N I/O
internal weak pull-up
LPLL_C_fb/RPLL_C_f
I Left/Right PLL feedback input pin, C(Comp)
b
LPLL_T_fb/RPLL_T_fb I Left/Right PLL feedback input pin, T(True)
LPLL_C_in/RPLL_C_i
I Left/Right PLL clock input pin, C(Comp)
n
LPLL_T_in/RPLL_T_in I Left/Right PLL clock input pin, T(True)
I, internal
GowinCONFIG mode selection pin, If this pin is not bonded
MODE2 weak pull-
out, it's internally grounded.
down
I, internal
GowinCONFIG mode selection pin, If this pin is not bonded
MODE1 weak pull-
out, it's internally grounded.
down
I, internal
GowinCONFIG mode selection pin, If this pin is not bonded
MODE0 weak pull-
out, it's internally grounded.
down

UG983-1.0E 7(11)
2 Overview Preliminary 2.6 I/O BANK Introduction

Pin Name I/O Description

Other Pins
VSS NA Ground pin
VCC NA Power supply pin of core voltage
VCCO# NA Power supply pin of I/O BANK# voltage.
VCCC NA Power supply pin of clock tree voltage
VCCX NA Power supply pin of auxiliary voltage
VCC_REG NA Power supply pin of Regulator voltage
Q*_VDD* NA Power supply pin of SerDes voltage
M*_VDD* NA Power supply pin of MIPI voltage
Note!
[1] Ready and Done should not be driven to low before and during configuration.

2.6 I/O BANK Introduction

GW5AT-138 includes 9 I/O Banks. See DS981, Arora V series of
FPGA Products Data Sheet for details.
This manual provides the pin distribution view of Arora V series of
FPGA products. For details, please refer to Chapter 3 View of Pin
Distribution. The I/O Banks that form Arora V series of FPGA products are
marked with different colors.
Various symbols and colors are used for the user I/O, power, and
ground. The various symbols and colors used for the various pins are
defined as follows:

 " " denotes the I/O in BANK0(Q0).

 " " denotes the I/O in BANK1(Q1).

 " " denotes the I/O in BANK2.

 " " denotes the I/O in BANK3.

 " " denotes the I/O in BANK4.

 " " denotes the I/O in BANK5.

 " " denotes the I/O in BANK6.

 " " denotes the I/O in BANK7.

 " " denotes the I/O in BANK10.

 " " denotes VCC, VCCX, and VCCO, and the filling color does not
change.

 " " denotes VSS, and the filling color does not change.

 " " denotes NC.

UG983-1.0E 8(11)
3 View of Pin Distribution Preliminary 3.1 View of GW5AT-138 Pins Distribution

3 View of Pin Distribution

3.1 View of GW5AT-138 Pins Distribution

3.1.1 View of FPG676A Pins Distribution
Figure 3-1 View of GW5AT-138 FPG676A Pins Distribution (Top View)

UG983-1.0E 9(11)
3 View of Pin Distribution Preliminary 3.1 View of GW5AT-138 Pins Distribution

Table 3-1 Other pins in GW5AT-138 FPG676A

VCCO2 V20,U23,T26,Y24,AC25,T16
VCCO3 R19,K24,N25,N15,P22,L21
VCCO4 F26,M18,J17,H20,G23,K14
VCCO5 C25,D22,F16,A21,B18,E19
VCCO6 J7,D2,F6,C5,A1,G3
VCCO7 M8,K4,P2,T6,L1,N5
VCCO10 W11,Y14
VCCX N9,L9,J9
L11,V10,P10,L13,K12,V12,K10,T12,M10,T1
VCC/VCCC
0,J11,J13,U11
VCC_REG C15,B8,B14,C7,B12,B10
Q1_VDDHA R9
Q0_VDDHA U9
Q1_VDDA/Q1_VDDD_IN0/Q1_VD
DD_IN1/Q1_VDDD_IN2/Q1_VDDD
_IN3/Q1_VDDTC/Q1_VDDTC_IN0/ AC9,AC13,AC11
Q1_VDDTC_IN1/Q1_VDDTC_IN2/
Q1_VDDTC_IN3
Q0_VDDA/Q0_VDDD_IN0/Q0_VD
DD_IN1/Q0_VDDD_IN2/Q0_VDDD
_IN3/Q0_VDDTC/Q0_VDDTC_IN0/ D11,D9,D13
Q0_VDDTC_IN1/Q0_VDDTC_IN2/
Q0_VDDTC_IN3
Q1_VDDT_IN0/Q1_VDDT_IN1/Q1
AA12,AA10
_VDDT_IN2/Q1_VDDT_IN3
Q0_VDDT_IN0/Q0_VDDT_IN1/Q0
F10,F12
_VDDT_IN2/Q0_VDDT_IN3
M0_VDDX/M1_VDDX M12
M0_VDDA/M0_VDDD/M1_VDDA/
N13,R13,U13,W13
M1_VDDD
M11,AE15,B15,A10,A12,A14,A16,A26,A6,A
8,AA14,AA16,AA26,AA6,AB10,AB12,AB14,
AB23,AB3,AA9,AB8,AC15,AC20,AC7,AD11
,AD13,AD6,AD9,AD16,AE24,AE4,AE6,AF1,
AF10,AF12,AF14,AF16,AF21,AF6,AF8,B16,
B23,B3,B6,C11,C13,C16,C20,C6,C9,D15,D
VSS 17,D7,E10,E12,E14,E24,E4,E7,E8,E9,F1,F
14,F21,F9,G10,G11,AB9,G13,Y12,G18,G12
,H25,H5,J12,J2,J22,K11,K13,K19,K9,L10,L
12,L16,L26,L6,M13,M23,M3,M9,N10,N20,P
13,P17,P7,P9,R10,R24,R4,T1,T11,T13,T21,
T9,U10,U12,U18,U8,V15,V25,V5,E15,W12,
W2,W22,Y11,Y10,Y13,Y19,V13

UG983-1.0E 10(11)
4 Package Diagram Preliminary

4 Package Diagram

4.1 FPG676A Package Outline (27mm x 27mm)

Figure 4-1 Package Outline FPG676A

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

A A
B B
C C
D D
E E
F F
G G
H H
J J
K K
L L
M M
N N
P P
R R
T T
U U
V V
W W
Y Y
AA AA
AB AB
AC AC
AD AD
AE AE
AF AF

6 5 4 3 2 1

A
B
C
D
E

UG983-1.0E 11(11)
Preliminary