Professional Documents
Culture Documents
07 May 2007
Revision 4.0
Contents
1.0 Introduction.................................................................................................................................... 4
1.1 LXT973 PHY Overview......................................................................................................... 4
2.0 LXD973TxFx Media Converter Board .......................................................................................... 5
2.1 Overview............................................................................................................................... 5
2.2 Features................................................................................................................................ 5
2.3 Functional Description .......................................................................................................... 5
2.4 FPGA .................................................................................................................................... 6
2.5 Configuration ........................................................................................................................ 7
2.5.1 Configuring the Duplex Mode .................................................................................. 7
2.5.2 Configuring the LEDs............................................................................................... 7
3.0 Operation........................................................................................................................................ 9
3.1 Evaluation Setup................................................................................................................... 9
4.0 LXD973TxFx Schematics ............................................................................................................10
Figures
1 LXD973TxFx Twisted-Pair-to-Fiber Media Converter Board ........................................................... 6
2 2 x 6 FIFO Block Diagram ............................................................................................................... 7
3 LXD973TxFx TX-to-FX 100 Mbps FD Media Converter (Top View) ............................................... 8
4 Power Control (Rev A2).................................................................................................................10
5 MII Ports - FIFO .............................................................................................................................11
6 TP Port 1 - Fiber Port 0 .................................................................................................................12
7 Board Power ..................................................................................................................................13
Tables
1 LXD973TxFx Jumper Configurations ..............................................................................................8
2 LXD973TxFx Bill of Materials (Rev A2) .........................................................................................14
Revision History
Revision 4.0
Revision Date: 07 May 2007
Revision 003
Revision Date: 10 October 10 2002
Revision 002
Revision Date: 01 February 2002
Modified Figure 1.
Modified Figure 3.
Replaced TP Port 1 - Fiber Port 0 schematic.
Modified Bill of Materials to reflect change in schematic.
1.0 Introduction
This application note is intended for system designers evaluating the
Cortina Systems® LXT973 Twisted-Pair-to-Fiber Media Converter Reference Design
(LXT973 PHY) to convert twisted-pair signals to/from fiber-optic signals.
This document provides details about the LXD973TxFx media converter board including
the following:
• Overview of the LXT973 PHY 2-Port Fast Ethernet PHY
• Media converter board features, functional description, configuration
• FPGA details (used in the conversion board design)
• Media converter board schematics
• Media converter board bill of materials
2.1 Overview
The LXD973TxFx is a simple low-cost board that demonstrates the ease of implementing
the LXT973 PHY in a media converter. The converter board uses off-the-shelf
components including the LXT973 PHY, Altera* EPM3064ALC44-4 FPGA, LEDs, and
associated control switches and jumpers.
2.2 Features
The following design and user features are incorporated into the LXD973TxFx media
converter board:
• Two IEEE 802.3 compliant ports
— 100BASE-TX
— 100BASE-FX
• Minimum configuration required
• Single 3.3 V power supply
• Auto MDI/MDIX on the 100BASE-TX port
• Three configurable LEDs for status display
TxCLK
FIFO RxCLK
LXT973 LXT973
Port 0 Port 1
RXD[ 0:3], RXER, RXDV TXD[ 0:3], TXER, TXEN
FIFO
RxCLK TxCLK
DPO DPI
DPO DPI
Transformer
FX
RJ-45
2.4 FPGA
A small buffer is required for each data direction. The data flowing from one MII port to the
other must be synchronized through a FIFO since the transmit and receive clocks on the
MII are both sourced by the PHY. The FPGA requires two 2 x 6 bit FIFOs between Port 1
and Port 0. The following parameters are used to calculate the FIFO depth:
• The MII clock is 25 MHz with a specification of +/-100 ppm.
• The maximum packet size is 1,518 bytes, which is 3,036 nibbles.
• Idle symbols on the line do not generate data across the MII, so the FIFO can
reposition its pointer after each packet.
• The clocks from each port are asynchronous.
The following seven MII signals are required on each side of the FIFO for data to flow
between the two ports:
• TXCLK
• TXD[3:0]
• TXEN
• TXER
• RXCLK
• RXD[3:0]
• RXDV
• RXER
An Altera* FPGA is used as the FIFO. Figure 2 provides FIFO implementation in VHDL
code in the FPGA (the VHDL code is available with this document).
6-Bit Register
E 1-Bit
Counter
Q D
RxCLK
6-Bit Register
2-Bit
TxCLK Counter
2.5 Configuration
3.0 Operation
Use the following steps for proper board operation:
1. Connect the power supply to the board power-plug
2. Set jumpers on JP1 as desired
3. Jumper pins 1 and 2 on JP1 for full-duplex operation (recommended) - default
4. Do not jumper pins 3 through 6 (for LED Mode – 1) - default
5. Plug in the power supply to a 110 volt wall outlet
6. Reset the board by depressing switch S1
7. Connect link partners with a twisted-pair cable to the RJ-45 connector (J1), and a fiber
optic cable to the fiber transceiver (F1)
8. Proceed with the evaluation
Caution: Operating the fiber side in full-duplex mode and the twisted-pair side in half-duplex mode
causes collisions and packet loss if both sides are trying to transmit and receive at the
same time.
Figure 4
LXD973TxFx
07 May 2007
Application Note
A B C D E
249945, Revision 4.0
U2C U2E
R1 4.7k 5 6 11 10
R2 4.7k
R3 4.7k
LED mode 1 2 3 4 R4 4.7k 74LVX14 74LVX14
74LVX14 74LVX14
VCC3_3 GND
GND
27
47
84
96
40
91
74
65
66
58
73
U1A
VCC3_3
VCCT
VCCT
VCCD
VCCD
VCCR
VCCR
X = DO NOT INSTALL
VCCIO
VCCIO
VCCIO
VCCIO
VCCPECL
R14 R13 R121 R122 R124
ADDR1 55 78 TxSLEW0 R125 X
ADDR2 ADDR1 TxSLEW0 TxSLEW1
Power Control (Rev A2)
2 1 MDIO1 23
4 3 LED_CFG0 11 22
LED_CFG1 LED_CFG0 MDC1
6 5 12 LED_CFG1
MDIO0 25
MDC0 26
HEADER 3X2 R49 R50 R123 RESETn
LXD973TxFx Schematics
13 RESET
4.7k 4.7k 4.7k R129 R20 R130 R19 R12 R11 R8 R5 R6
56 15 REFCLK
TEST_0 REFCLK 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k 4.7k
57 TEST_1
VCC3_3
GND
28
48
83
95
16
41
90
77
61
70
62
69
14
GND GND
D1 R21
10K
2 1N914 2
U2A U2B
S1 R22
1 2 3 4 GND VCC3_3
SW NO 100
74LVX14 74LVX14 C40 0.1uF
+ C1
10uF TANT Y1
GND 14 1
GND VCC NC
CAPS FOR THE LXT973
VCCD2_5 VCCA2_5 VCC3_3
R107
REFCLK 8 7
OUT GND
49.9
25MHzCRYSTAL OSC
GND
C4 C5 C8 C9 C10 C11 C6 C7 C51 C52 C53 C54
1 0.1uF .001uF 0.1uF .001uF 0.1uF .001uF 0.1uF .001uF 0.1uF .001uF 0.1uF .001uF 1
CONTROL/POWER
Title
GND GND GND
LXT973 Media Converter
Size Document Number Rev
B A2
Page 10
4.0 LXD973TxFx Schematics
Figure 5
LXD973TxFx
07 May 2007
Application Note
A B C D E
249945, Revision 4.0
U3 CAPS VCC3_3
VCC3_3 VCC3_3
D2 R108 220
3
23
15
35
U3 EPM3064A
4 C34 C35
PORT 0 LED GREEN 4
0.1uF 0.1uF
U1B D3 R109 220
VCCIO
VCCIO
VCCINT
VCCINT
LED GREEN
18 9 RXD0_3 29 49
RXD_1_3 RXD_0_3 RXD0_3 LED0_1
MII Ports - FIFO
7 TDI
3 TDI SD0 3
13 TMS LXT973
TMS TDO
TDO 38
32 TCK R91 82
TCK
GND
GND
GND
GND
GND
GND
GND
GND
GND
1
10
17
22
30
36
42
44
VCC3_3 VCCA2_5
LED GREEN
RXD1_3 85 82
RXD1_2 RXD1_3 LED1_1 D7 R116 220 R83 R136
2 86 81 2
RXD1_1 RXD1_2 LED1_2 49.9 49.9
87 RXD1_1 LED1_3 80
RXD1_0 88 LED GREEN
RXDV1 RXD1_0
89 RXDV1
RXCLK1 92 67 DPBP_0 C59
RXER1 RXCLK1 DPBP_1 DPBP_1 FX_BP_0
93 RXER1
TXER1 94 68 0.01uF
TXCLK1 TXER1 DPBN_1 DPBN_1
97 DPBN_0 C60
TXEN1 TXCLK1 FX_BN_0
98 TXEN1
TXD1_0 99 71 0.01uF
TXD1_1 TXD1_0 DPAP_1 DPAP_1
100 TXD1_1
TXD1_2 1 72
TXD1_3 TXD1_2 DPAN_1 DPAN_1
2 TXD1_3
VCC3_3 3 COL1
4 CRS1 SD1 75
LXT973
R131 R132 R133 R134
1K 1K 1K 1K GND
JP2
1 2 1 TCK 1
4 3 TDO
6 5 TMS
8 7
10 9 TDI MII PORTS AND FIFO
Title
HEADER 5X2
LXT973 Media Converter
GND Size Document Number Rev
B A2
Page 11
4.0 LXD973TxFx Schematics
Figure 6
LXD973TxFx
07 May 2007
Application Note
A B C D E
249945, Revision 4.0
VCCA2_5
DPAN_1 TP PORT 1
DPAP_1
FB1
4 DPBN_1 4
Ferrite Bead T1
DPBP_1
J1 RJ-45
DPBP_1 16 1 BP_1
BN_1 1
AP_1 2
15 2 3
FX_AN_0 4
DPBN_1 14 3
FX_AP_0 5
AN_1
FX_BN_0 6
FX_BP_0 7
S1
S2
8
SD0 DPAP_1 11 6
9
10
HALO TG110-S050N2
C24
0.01uF
R117 R118
3
0 0 3
GND R96 R97
49.9 49.9
C22 C23
0.001uF 2KV 0.001uF 2KV
C25
0.001uF 2KV
VCC3_3
FIBER PORT 0
2 2
VCC3_3
GND
C20 F1
+
6 5 FX_AP_0
0.1uF TX Vcc RD
C57 R137 R138 7 4 FX_AN_0
0.01uF 1.3K 1.3K TX Gnd RD
8 3 SD0
N/C SD
GND GND
FX_BP_0 9 2
TD RX Vcc R90 R89
FX_BN_0 10 1 130 130
TD RX Gnd
+ C21
0.1uF
R139 R140 FIBER PORT
2K 2K
1 GND GND 1
HFBR_5903
GND
TP PORT 1/FIBER PORT 0
Title
LXT973 Media Converter
Size Document Number Rev
B A2
Page 12
4.0 LXD973TxFx Schematics
Figure 7
LXD973TxFx
07 May 2007
Application Note
A B C D E
249945, Revision 4.0
4 4
Board Power
VR1
3
MIC39100-2.5BS 3
TAB IS GROUND
VIN
GND
VOUT
VCC3_3
1
2
3
VCC3_3IN VCC3_3 VCCD2_5
FB3
VCCA2_5 D8
Large Ferrite BOARD
J2 FB2 FB4 LED GREEN
POWER C55
3.5 mm POWER JACK Large Ferrite Ferrite Bead
0.001uF 2KV
3.3v, 3A WALL + C32 + C45 + C46 + C43 + C47 R112 C56
2 2
GND GND
GND
LXT973 CORE VOLTAGES = 2.5V
1 1
Page 13
4.0 LXD973TxFx Schematics
LXD973TxFx 5.0 LXD973TxFx Bill of Materials
Application Note
249945, Revision 4.0
07 May 2007
~ End of Document ~