5/8/2019 Sequence Detector using Mealy and Moore State Machine VHDL Codes

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Sequence Detector using Mealy and Moore State Machine VHDL Codes
July 5, 2017 by shahul akthar

Mealy State Machine

The Output of the state machine depends on both present state and current input. When the input changes,the output of the state machine

updated without waiting for change in clock input.

Moore State Machine

The Output of the State machine depends only on present state. The output of state machine are only updated at the clock edge. 

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5/8/2019 Sequence Detector using Mealy and Moore State Machine VHDL Codes

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Let’s construct the sequence detector for the sequence 101 using both mealy state machine and moore state machine.

Moore state require to four states st0,st1,st2,st3 to detect the 101 sequence.

Mealy state machine require only three states st0,st1,st2 to detect the 101 sequence.

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5/8/2019 Sequence Detector using Mealy and Moore State Machine VHDL Codes

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VHDL code for Sequence detector (101) using moore state machine

1 library IEEE;
2 use IEEE.STD_LOGIC_1164.ALL;
3
4 entity moore is
5 Port ( clk : in STD_LOGIC;
6 din : in STD_LOGIC;
7 rst : in STD_LOGIC;
8 dout : out STD_LOGIC);
9 end moore;
10
11 architecture Behavioral of moore is
12 type state is (st0, st1, st2, st3);
13 signal present_state, next_state : state;
14 begin
15
16 synchronous_process: process (clk)
17 begin
18 if rising_edge(clk) then
19 if (rst = '1') then
20 present_state <= st0;
21 else
22 present_state <= next_state;
23 end if;
24 end if;
25 end process; 
26
27 output_decoder : process(present_state, din)
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5/8/2019 Sequence Detector using Mealy and Moore State Machine VHDL Codes

28 begin
29 next_state <= st0; case (present_state) is when st0 =>
30 if (din = '1') then
31 next_state <= st1;
32 else
33 next_state <= st0; end if; when st1 =>
34
 Menu if (din = '1') then 
35 next_state <= st1;
36 else
37 next_state <= st2; end if; when st2 =>
38 if (din = '1') then
39 next_state <= st3;
40 else
41 next_state <= st0; end if; when st3 =>
42 if (din = '1') then
43 next_state <= st1;
44 else
45 next_state <= st2; end if; when others =>
46 next_state <= st0; end case; end process; next_state_decoder : process(present_state) begin case
(present_state) is when st0 =>
47 dout <= '0'; when st1 =>
48 dout <= '0'; when st2 =>
49 dout <= '0'; when st3 =>
50 dout <= '1'; when others =>
51 dout <= '0';
52 end case;
53 end process;
54
55 end Behavioral;

VHDL code for Sequence detector (101) using mealy state machine

1 library IEEE;
2 use IEEE.STD_LOGIC_1164.ALL;
3
4 entity mealy is
5 Port ( clk : in STD_LOGIC;
6 din : in STD_LOGIC;
7 rst : in STD_LOGIC;
8 dout : out STD_LOGIC);
9 end mealy; 
10

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5/8/2019 Sequence Detector using Mealy and Moore State Machine VHDL Codes

11 architecture Behavioral of mealy is

12 type state is (st0, st1, st2, st3);
13 signal present_state, next_state : state;
14 begin
15
16 syncronous_process : process (clk)
17
 Menu begin 
18 if rising_edge(clk) then
19 if (rst = '1') then
20 present_state <= st0;
21 else
22 present_state <= next_state;
23 end if;
24 end if;
25 end process;
26
27 next_state_and_output_decoder : process(present_state, din)
28 begin
29 dout <= '0'; case (present_state) is when st0 =>
30 if (din = '1') then
31 next_state <= st1;
32 dout <= '0';
33 else
34 next_state <= st0;
35 dout <= '0'; end if; when St1 =>
36 if (din = '1') then
37 next_state <= st1;
38 dout <= '0';
39 else
40 next_state <= st2;
41 dout <= '0'; end if; when St2 =>
42 if (din = '1') then
43 next_state <= st1;
44 dout <= '1';
45 else
46 next_state <= st0;
47 dout <= '0'; end if; when others =>
48 next_state <= st0;
49 dout <= '0';
50 end case;
51 end process; 
52
53 end Behavioral;
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5/8/2019 Sequence Detector using Mealy and Moore State Machine VHDL Codes

TestBench VHDL code for sequence detector using Moore State Machine

1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3
4 ENTITY tb_moore IS
 Menu
5 END tb_moore; 
6
7 ARCHITECTURE behavior OF tb_moore IS
8
9 -- Component Declaration for the Unit Under Test (UUT)
10
11 COMPONENT moore
12 PORT(
13 clk : IN std_logic;
14 din : IN std_logic;
15 rst : IN std_logic;
16 dout : OUT std_logic
17 );
18 END COMPONENT;
19
20 --Inputs
21 signal clk : std_logic := '0';
22 signal din : std_logic := '0';
23 signal rst : std_logic := '0';
24
25 --Outputs
26 signal dout : std_logic;
27
28 -- Clock period definitions
29 constant clk_period : time := 20 ns;
30
31 BEGIN
32
33 -- Instantiate the Unit Under Test (UUT)
34 uut: moore PORT MAP (
35 clk => clk,
36 din => din,
37 rst => rst,
38 dout => dout
39 );

40

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5/8/2019 Sequence Detector using Mealy and Moore State Machine VHDL Codes

41 -- Clock process definitions

42 clk_process :process
43 begin
44 clk <= '0';
45 wait for clk_period/2;
46 clk <= '1';
47
 Menu wait for clk_period/2; 
48 end process;
49
50 -- Stimulus process
51 stim_proc: process
52 begin
53
54 rst <= '1';
55
56 wait for 100 ns;
57
58 rst <= '0';
59
60 din <= '0';
61
62 wait for 20 ns;
63
64 din <= '1';
65
66 wait for 20 ns;
67
68 din <= '0';
69
70 wait for 20 ns;
71
72 din <= '1';
73
74 wait for 20 ns;
75
76 din <= '0';
77
78 wait for 20 ns;
79
80 din <= '1';
81 
82 wait for 20 ns;
83
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5/8/2019 Sequence Detector using Mealy and Moore State Machine VHDL Codes

84 din <= '0';

85
86 wait for 20 ns;
87
88 din <= '1';
89 end process;
90
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91 END;

Note: Same testbench code can be used for Mealy VHDL code by simply changing the component name to mealy.

TestBench output waveform for Mealy and Moore State Machine

From the above shown waveform, sequence 101 is detected twice from the testbench VHDL code.

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2 thoughts on “Sequence Detector using Mealy and Moore State Machine VHDL Codes”

nia
November 8, 2017 at 1:48 am | Reply

Thanks, very helping. this working

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5/8/2019 Sequence Detector using Mealy and Moore State Machine VHDL Codes

coder
September 1, 2017 at 11:56 pm | Reply

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hello, mealy machine is not working good, the dout becomes ‘1’ on falling edge of clock and not rising edge. thanks

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