Scribd Logo
Upload

Welcome to Scribd!

  • VLSI Model qp2

    Uploaded by

    M. Thirumala Reddy
    20 views1 page
    A full adder has three inputs (a, b, cin) and two outputs (s, cout) where s is the sum and cout is the carry-out. The formulae for s and cout can be expressed in disjunctive normal form. There are three approaches for handling carry in n-bit word adders: (1) ripple carry which has a delay that increases linearly with word size, (2) carry-skip with fixed-size blocks which can reduce delay but requires multiple blocks, and (3) carry-skip with variable-size blocks which can further reduce delay but is more complex to implement. The document estimates and compares the delays of implementing a 48-bit adder using each

    Original Description:

    Original Title

    VLSI model qp2

    Copyright

    © © All Rights Reserved

    Available Formats

    PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    Report this Document
    A full adder has three inputs (a, b, cin) and two outputs (s, cout) where s is the sum and cout is the carry-out. The formulae for s and cout can be expressed in disjunctive normal form. There are three approaches for handling carry in n-bit word adders: (1) ripple carry which has a delay that increases linearly with word size, (2) carry-skip with fixed-size blocks which can reduce delay but requires multiple blocks, and (3) carry-skip with variable-size blocks which can further reduce delay but is more complex to implement. The document estimates and compares the delays of implementing a 48-bit adder using each

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    20 views1 page

    VLSI Model qp2

    Uploaded by

    M. Thirumala Reddy
    A full adder has three inputs (a, b, cin) and two outputs (s, cout) where s is the sum and cout is the carry-out. The formulae for s and cout can be expressed in disjunctive normal form. There are three approaches for handling carry in n-bit word adders: (1) ripple carry which has a delay that increases linearly with word size, (2) carry-skip with fixed-size blocks which can reduce delay but requires multiple blocks, and (3) carry-skip with variable-size blocks which can further reduce delay but is more complex to implement. The document estimates and compares the delays of implementing a 48-bit adder using each

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 1

    2008 Paper 9 Question 2

    VLSI Design

    (a) A full adder for a single bit has three inputs, a, b and cin , and two outputs,
    s and cout for the sum and carry-out. State the formulae for s and cout in
    disjunctive normal form. [2 marks]

    (b) Explain the operation of the following three approaches for handling carry in
    n-bit word adders, deriving formulae for the signals involved and explaining
    the limiting factors on their speed:

    (i ) ripple carry, [2 marks]

    (ii ) carry-skip with fixed-size blocks, and [6 marks]

    (iii ) carry-skip with variable-size blocks. [4 marks]

    (c) Assuming a delay of τ for a round of combinational logic consisting of negation,


    conjunction and disjunction, estimate the delays for the three designs applied
    to a 48-bit adder. [3 × 2 marks]

    You might also like