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  • Vlsi QP11

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    M. Thirumala Reddy
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    The document discusses different designs for an n-input NAND gate in CMOS technology, including static CMOS, dynamic CMOS, and pseudo-nMOS. It asks the reader to sketch each design, annotate with suitable transistor widths considering resistance differences between p-channel and n-channel transistors, and calculate logical effort and parasitic delay for each. It then asks which design would be fastest for an n=4 input NAND gate when resistance of p-channel is 3 times n-channel, and how the answer might change if driving a large capacitive load.

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    VLSI QP11

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    The document discusses different designs for an n-input NAND gate in CMOS technology, including static CMOS, dynamic CMOS, and pseudo-nMOS. It asks the reader to sketch each design, annotate with suitable transistor widths considering resistance differences between p-channel and n-channel transistors, and calculate logical effort and parasitic delay for each. It then asks which design would be fastest for an n=4 input NAND gate when resistance of p-channel is 3 times n-channel, and how the answer might change if driving a large capacitive load.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Flag for inappropriate content
    9 views1 page

    Vlsi QP11

    Uploaded by

    M. Thirumala Reddy
    The document discusses different designs for an n-input NAND gate in CMOS technology, including static CMOS, dynamic CMOS, and pseudo-nMOS. It asks the reader to sketch each design, annotate with suitable transistor widths considering resistance differences between p-channel and n-channel transistors, and calculate logical effort and parasitic delay for each. It then asks which design would be fastest for an n=4 input NAND gate when resistance of p-channel is 3 times n-channel, and how the answer might change if driving a large capacitive load.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    2004 Paper 9 Question 2

    VLSI Design

    (a) Sketch designs for an n-input NAND gate in CMOS using

    (i ) static CMOS;

    (ii ) dynamic CMOS;

    (iii ) pseudo-nMOS. [2 marks each]

    (b) Assuming that a conducting p-channel has a resistance γ times that of a


    similarly sized n-channel, annotate each of your circuit diagrams with suitable
    widths for the transistors, and explain the reasons for their values.
    [2 marks each]

    (c) For each design, calculate the logical effort and the parasitic delay.
    [2 marks each]

    (d ) Which is likely to be fastest for the case when n = 4 and γ = 3? What


    difference would it make if the circuit were driving a large capacitative load?
    [2 marks]

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